Abstract

In this paper, the optimal transistor sizing of the digital cells has been obtained using Simulated Annealing algorithm and an Artificial Bee Colony algorithm and their results have been compared with nominal results for various nanoscale CMOS digital circuits. The goal is to minimize the leakage power keeping the other performance parameters such as propagation delays and the area in the bound. The simulations are done using HSPICE tool for 45nm and below using Metal gate High k Predictive Technology Model cards. To make sure of the unaffected working of all cells in the automotive applications, the temperature range and supply voltage has been taken between −55oC to 125oC and 0.95V to 1.05V respectively. The Overall reduction in leakage power achieved in the logic cells is up to 70% without any penalty in the critical path delay.

Abstract

In this paper, a highly stable all CMOS current reference against temperature and supply variation is proposed. Current reference of 5µA and 50nA has been designed for low power and ultra-low power applications respectively. The reference architecture is based on ratio between the PTAT voltage and the PTAT resistance. The process insensitive temperature compensation is accomplished by dividing TC of voltage with process insensitive TC of resistor. A high PSRR, process independent voltage reference is designed for PTAT voltage. N-poly on chip resistor is used for PTAT resistance. The proposed current reference is implemented in 0.18-µm TSMC technology. The architecture achieved PSRR of 74dB and line sensitivity of 0.05% works at supply voltage variation from 1.4V to 3.6V. The current reference of 5µA and 50nA attain temperature coefficient of 11.6 ppm/oC and 12.2 ppm/oC respectively for the temperature variation of -55oC to 125oC.

Abstract

Domain Specific Modeling Languages (DSML) significantly improve productivity in designing Computer Based System (CBS), by enabling them to be modeled at higher levels of abstraction. It is common for large and complex systems with distributed teams, to use DSMLs, to express and communicate designs of such systems uniformly, using a common language. DSMLs enable domain experts, with no or minimal software development background, to model solutions, using the language and terminologies used in their respective domains. Although, there are already a number of DSMLs available for modeling CBSs, their need is felt strongly across multiple domains, which still are not well supported with DSMLs. Developing a new DSML, however, is non trivial, as it requires (a) significant knowledge about the domain for which the DSML needs to be developed, as well as (b) skills to create new languages. In the …

Abstract

Enormous increase in process variations (due to progressive CMOS technology scaling) along-with the temperature and supply voltage variations are severely degrading the fabrication outcome of digital circuits i.e. circuits are not accomplishing the specification bounds of the required performances. Therefore, process and operating variations aware optimization has become a very essential task in VLSI design. Moreover, many specifications in a circuit have challenging trade-offs, hence demand effective optimization skills. With this vision, this paper presents optimization algorithm based robust transistor sizing for various nanoscale CMOS digital circuits. The objective is to minimize the static i.e. leakage power without degrading the operating frequency (i.e. keeping the propagation delays in bound) and area. The reported results are shown for 32nm CMOS Metal gate High-k model parameters, however methodology is equally valid for further scaled technology nodes. The Overall reduction in leakage power obtained is up to 88% keeping bound on the critical path delay. The temperature range and supply voltage has been taken between −55◦C to +125◦C (for automotive applications) and 0.90V to 1.10V (±10% variations) respectively at 3-sigma design.

Abstract

With the technology scaling down to sub-50 nm regime, the necessity of process variation aware estimation of Leakage Power is emphasized for robust digital circuit design. Variations in Leakage power results in a large increase in the variation of total power dissipation. This paper presents a Regression based estimation of leakage powers and total power dissipation in nanoscale standard cell-based designs that show an impressive speed-up advantage with respect to analog SPICE-level simulation. We propose a statistical variation aware estimation model through a Multivariate Linear Regression (MLR) and Multivariate Polynomial Regression (MPR) techniques. Exhaustive tests report shows MPR technique outperforms MLR technique in estimating the leakage and total power for the targeted 16 nm CMOS technology with negligible error (<1%). The proposed methodology works as black box i.e. equally valid for 16 nm, 22 nm and 45 nm technology nodes.

Abstract

Student internships are necessary for every student to learn and apply the learning to deliver tangible and relevant outcomes. In-person internship opportunities are less in number and have major challenges in scaling such as lesser number of available projects in relevant technologies, inadequate mentorship during the internship, varying college calendars and others. This paper presents SRIP (Student Remote Internship Program) approach which focuses on the domain of programming in open source technologies and projects for the internships that are relevant to 2nd and 3rd year engineering college students. It aims to overcome the stated challenges and simultaneously make a contribution to the open source community. Virtual Labs is the open source repository that we leveraged to implement SRIP pilot study for interns to contribute and develop programming skills.

Abstract

A sub 1−V , ultra low power temperature sensor has been implemented in TSMC 180 nm. The architecture is digital friendly since it creates a pulse width modulated wave instead of voltage. It uses proportional to absolute temperature(PTAT) characteristics of resistance to generate PTAT delay. Temperature to delay conversion depends only on passive elements, thereby making the circuit insensitive to supply variations. Line sensitivity of 0.23 ◦C/V is achieved for a wide supply range of 0.7−3.6 V . A non linearity error of less than 0.8 ◦C is measured for −55 to 125 ◦C using linear fit curve. This occupies an area of 0.82 mm2 and consumes a power of 47 nW at 0.8 V supply.

Abstract

Virtual Labs is an MHRD (Ministry of Human Resource Development, India) initiative in which over 1100 virtual experiments are freely available to engineering students across India and the rest of the globe to access and learn. Until the beginning of 2018, the lab usages by students were mostly in the push mode during the workshops. The average usage per workshop was significantly low, at about 8 usages per student. Interventions were proposed in the process to improve the usage by enhancing 'Arousal' and 'Choices' as students' motivation. Qualitative observation of the results shows that students conducted more than the requested 15 experiments, along with the expectation of instant appreciation and recognition. This change in the process to create extrinsic motivation increased the usage per student from 8.62 to 19.7. self-reported motivation levels of students after doing the experiments improved from 5 to …

Abstract

Due to the advent of deep sub-micron technologies, statistical (in addition to temperature and supply voltage) variations aware estimation of leakages power has become prominent. Also, estimation of leakage currents at SPICE level guarantees the most accurate results, however not feasible means in high complexity ICs. This performs adversely for Monte-Carlo iterations for statistical analysis. In this paper we introduced an accurate machine learning technique to model statistical and operating variation aware estimation from Artificial Neural Network and regression based Multivariate Polynomial Regression which exhibits innately faster computation and attained error less than 1% for the targeted 16nm FinFET technology node although model is black box for any technology. The accuracy of the proposed technique has been tested over several basic cells and estimation of the complex circuits have been carried out utilizing the pre-modelled basic cells.

Abstract

India graduates 1.5 million engineering students every year, majority of them from its Tier 2 and Tier 3 colleges where there is severe shortage of qualified faculty and lab infrastructure, and where English is second or third language for most students. To provide affordable virtual laboratories to these engineering colleges, Government of India runs the Virtual Labs project with a select set of participating institutions to create virtual labs required for entire engineering student population of India. The program suffers from two problems: 1) lack of focus on pedagogy and learnability of labs being created, and 2) little ability to scale to more teachers and subject matter experts to produce labs aligned to local contexts. This paper presents a model (LEAD model) for the design of virtual labs for a data structures and algorithms course in computer science and is intended to address the problems stated above. The model …