Abstract

This brief presents a CMOS-only ultra low power voltage reference of 0.925V which is designed and simulated in TSMC 180nm technology. Current mixing between SelfBiased Self Cascode MOSFET (SBSCM) and Self Cascode MOSFET (SCM) pair is introduced along with stacking of proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltage generators to get second order curvature compensation. Temperature coefficient (TC) of 3.75ppm/°C over a wide temperature range of -55°C to 140°C is achieved. To feed on the power reduction requirement of low power biomedical applications, the entire circuit is designed in sub-threshold region. Therefore, the total power consumption is 27nW @ 1.45V at room temperature (27°C). Furthermore, a supply independent current bias aids in realizing high PSRR of -91dB @ 10Hz / -50dB @ 100MHz and line regulation of 0.0779%/V over a supply range 1.45V to 3.6V. Besides, an employed trimming technique attenuates the process spread from ±3% to ±0.3%. Moreover, the proposed design occupies an active area of 0.0054mm 2 only.

Abstract

This brief presents a novel PVT-invariant CMOS relaxation oscillator for Real-Time Clock (RTC) applications. The proposed design is compatible to work in a low supply voltage domain of SoC. The PVT invariance is achieved by a unique circuit implementation of introducing a self-adaptive mechanism that dynamically modifies the time constant of the oscillator core. Moreover, the design is accompanied by a digital calibration unit for further process compensation. Besides, the introduced supply independent bias circuit has greatly improved the supply regulation of the oscillator frequency. In addition, the design utilizes a complementary to absolute temperature (CTAT) current for temperature compensation. Area efficiency is enhanced by replacing bigger passive device i.e, resistor with an adaptive MOS resistor. The obtained results show that the minimum temperature coefficient (TC) of 31.236ppm/°C is achieved over a range of -40°C to 100°C. The resultant phase noise of -140dBc/Hz@1MHz is observed. The design has achieved a good power efficiency of 1.65nW/KHz at room temperature without a calibration unit. The line sensitivity (LS) of 0.1159%/V is noted in the range of 0.7V to 1.2V. Nevertheless, the entire system occupies an active area of 0.0509mm^2 with a power consumption of 90nW@0.7V. Also, the leakage current of the complete system is <; 54pA. Therefore, the proposed design aims at providing a production-friendly, ease of integration and low-cost solution.

Abstract

he paper presents an eight transistor (8T) pico-watt current reference with a novel method of rectifying the prob-lem of exponential power increase w.r.t temperature in traditionalsub-nW references. The proposed current reference is obtainedby modifying the traditional beta-multiplier architecture to scale-down the power consumption without sacrificing area. Theconstancy of power consumption w.r.t temperature is achievedby exploiting the voltage-current characteristics of a leakagetransistor in the modified architecture. The proposed currentreference, implemented in UMC 55nm technology, occupies anarea of0.00035mm2. It is designed for a current of 60pA andachieves an accuracy of19ppm/0Cover a wide temperaturerange of−550Cto1250C. The reported line sensitivity for thecurrent reference is 0.07%/V in the supply range of 1.2V - 4V.Post-trim results show a constant power consumption of 144pWw.r.t temperature and process variations @1.2V supply.

Abstract

This paper presents a robust short-term electrical load forecasting framework that can capture variations in building operation, regardless of building type and location. Nine different hybrids of recurrent neural networks and clustering are explored. The test cases involve five commercial buildings of five different building types, i.e., academic, research laboratory, office, school and grocery store, located at five different locations in Bangkok-Thailand, Hyderabad-India, Virginia-USA, New York-USA, and Massachusetts-USA. Load forecasting results indicate that the deep learning algorithms implemented in this paper deliver 20–45% improvement in load forecasting performance as compared to the current state-of-the-art results for both hour-ahead and 24-ahead load forecasting. With respect to sensitivity analysis, it is found that: (i) the use of hybrid deep learning algorithms can take as less as one month of data to …

Abstract

In this paper, we propose an accurate and computationally efficient Gradient Boosting approach for the estimation of statistical variations aware leakage power and propagation delay in the CMOS/FinFET standard digital cells. The proposed model estimates the leakage power and propagation delay w.r.t variations in process, temperature (−55°C to 125°C) and supply voltage(±10% variations). The distinguishing feature of the proposed approach is its compatibility with both CMOS and FinFET technologies. Moreover, the performance of the proposed model is consistent with various technology nodes. Exhaustive tests report an average error of <1% in 16nm CMOS and FinFET standard digital cells w.r.t analog HSPICE simulations with several orders increase in computational speed. Further, the complex cell estimation can be carried out through precharacterized standard cells abstaining longer simulations.

Abstract

Rapid urbanization and associated land-use changes in cities cause an increase in the demand for electricity by altering the local climate. The present study aims to examine the variations in total energy and cooling energy demand in a calibrated building, caused by urban heat island formation over Delhi. The study used Sentinel-2A multispectral imagery for land use and land cover (LULC) of mapping of Delhi, and Moderate Resolution Imaging Spectroradiometer (MODIS) imagery for land surface temperature (LST) mapping during March 2018. It was observed that regions with dense built-up areas (ie, with built-up area greater than 90%) had a higher annual land surface temperature (LST), ie, 293.5 K and urban heat island intensity (UHII) ranging from 0.9 K-5.9 K. In contrast, lower annual values of LST (290K) and UHII (0.0-0.4 K) were observed in regions with high vegetation cover (53%). Statistical analysis reveals that a negative correlation exists between vegetation and nighttime LST, which is further confirmed by linear regression analysis. Energy simulations were performed on a calibrated building placed at three different sites, identified on the basis of land use and land cover percentage and annual LST. Simulation results showed that the site located in the central part of Delhi displayed higher annual building energy consumption (425.12 MWh/y) compared to the site located in the rural periphery (381.13 MWh/y). For all the three sites, the maximum electricity consumption and the cooling load were observed in the summer season, while the minimum were seen in the winter season. The study indicates that UHI formation leads to …

Abstract

Approximate Computing has paved way for elaborate savings in design area and latency of modern system architectures processing images or signals, by a deliberate yet tolerable loss of functional accuracy. This paper thus proposes a design of an approximate multiplier based on the efficient Toom-Cook algorithm, that has a lower complexity of O(N logd(zd−1) ) than O(N 2 ), for order d. Inherent integer divisions in the algorithm has restricted its feasibility in hardware, unless without suitable approximation. On an average, the proposed multiplier achieves 53%, 18% and 57% improvements in area, delay and power only with less than 1% mean error. Owing to these benefits due to lower computational complexity, the multiplier can be configured to achieve significant savings with a high quality output and that suits well to the nature of the speech processing systems, hence the design works well for the epoch extraction system in speech.

Abstract

This brief presents a novel low-power and area-efficient LDO that satisfies all primary requirements of power mapping for a Power Management IC (PMIC). The design introduces a dynamically biased feedback resistor which responds instantly to the output voltage variations, thereby achieving better load transient behavior. Besides, the employed adaptive-biasing technique contributes in architectural transformation to attain stability over a wider range of load currents (0–100mA). It provides a regulated voltage of 1.87V from a supply ranging from 1.92V to 3.6V with a reported load and line regulation of 0.00136mV/mA and 0.078mV/V respectively. Moreover, the circuit potentially supports the load transients either from 0A to 100mA or 100mA to 0A with a rise and fall times of 10 μs. The achieved overshoot and undershoot values are 160mV and 154mV respectively. Hence, it demonstrates a substantial steady-state and transient performance with low-power thus making it suitable for battery-operated portable devices.

Abstract

Construction of buildings without keeping enough setback from plot boundary is very common practise in India. This lead to very closely spaced buildings with practically zero or few mm gap between them. The intension behind this is to utilize the maximum plot area, without knowing the consequences of damage due to pounding during moderateto-severe earthquake shaking. In this study, an attempt is made to check the adequacy of separation distance clause of IS 1893: 2016 and also a comparison is made with similar clauses in international codes of practise. For this purpose, four low to mid-rise RC buildings located in seismic zone IV were designed as per IS 456: 2000 and IS 1893: 2016. These buildings are assumed to be closely spaced with each other, in pair of two, for four different cases. Further, the linear and non-linear time history analysis (NLTHA) were carried out by considering ground motion time histories of three moderate earthquakes recorded in India. From the study, it was found that the separation distance clauses prescribed in IS 1893-2016 are on conservative side.

Abstract

This work presents a highly accurate current reference of 66nA for ultra-low power applications. A very low figure-of-merit (FOM) of 1.3501ppm/°C 2 is achieved on consuming a minimal quiescent current of 199.37nA. To cancel out process variations, the current subtraction technique is employed and a β-multiplier is used to compensate for mobility (μ) and threshold voltage (V th ). In addition, curvature compensation technique backed by PTAT and CTAT current cancellation is adopted to attain a lower temperature coefficient (TC). Hence, an imperceptible variation of accuracy with temperature and supply variations across all process corners is attained. An adopted trimming scheme further minimizes the overall process spread to ±1.515% without compromising on accuracy. Accordingly, a TC of 67.04ppm/°C over a wide temperature range of −50° C to 100° C is obtained. Furthermore, 1.413%/V line sensitivity (LS) in the supply range of 1.38V to 3V is observed. Low power consumption of 275.13nW@1.38V facilitates its use in high-performance low power applications.