Abstract

With the technology scaling down to sub-50 nm regime, the necessity of process variation aware estimation of Leakage Power is emphasized for robust digital circuit design. Variations in Leakage power results in a large increase in the variation of total power dissipation. This paper presents a Regression based estimation of leakage powers and total power dissipation in nanoscale standard cell-based designs that show an impressive speed-up advantage with respect to analog SPICE-level simulation. We propose a statistical variation aware estimation model through a Multivariate Linear Regression (MLR) and Multivariate Polynomial Regression (MPR) techniques. Exhaustive tests report shows MPR technique outperforms MLR technique in estimating the leakage and total power for the targeted 16 nm CMOS technology with negligible error (<1%). The proposed methodology works as black box i.e. equally valid for 16 nm, 22 nm and 45 nm technology nodes.

Abstract

Student internships are necessary for every student to learn and apply the learning to deliver tangible and relevant outcomes. In-person internship opportunities are less in number and have major challenges in scaling such as lesser number of available projects in relevant technologies, inadequate mentorship during the internship, varying college calendars and others. This paper presents SRIP (Student Remote Internship Program) approach which focuses on the domain of programming in open source technologies and projects for the internships that are relevant to 2nd and 3rd year engineering college students. It aims to overcome the stated challenges and simultaneously make a contribution to the open source community. Virtual Labs is the open source repository that we leveraged to implement SRIP pilot study for interns to contribute and develop programming skills.

Abstract

A sub 1−V , ultra low power temperature sensor has been implemented in TSMC 180 nm. The architecture is digital friendly since it creates a pulse width modulated wave instead of voltage. It uses proportional to absolute temperature(PTAT) characteristics of resistance to generate PTAT delay. Temperature to delay conversion depends only on passive elements, thereby making the circuit insensitive to supply variations. Line sensitivity of 0.23 ◦C/V is achieved for a wide supply range of 0.7−3.6 V . A non linearity error of less than 0.8 ◦C is measured for −55 to 125 ◦C using linear fit curve. This occupies an area of 0.82 mm2 and consumes a power of 47 nW at 0.8 V supply.

Abstract

Virtual Labs is an MHRD (Ministry of Human Resource Development, India) initiative in which over 1100 virtual experiments are freely available to engineering students across India and the rest of the globe to access and learn. Until the beginning of 2018, the lab usages by students were mostly in the push mode during the workshops. The average usage per workshop was significantly low, at about 8 usages per student. Interventions were proposed in the process to improve the usage by enhancing 'Arousal' and 'Choices' as students' motivation. Qualitative observation of the results shows that students conducted more than the requested 15 experiments, along with the expectation of instant appreciation and recognition. This change in the process to create extrinsic motivation increased the usage per student from 8.62 to 19.7. self-reported motivation levels of students after doing the experiments improved from 5 to …

Abstract

Due to the advent of deep sub-micron technologies, statistical (in addition to temperature and supply voltage) variations aware estimation of leakages power has become prominent. Also, estimation of leakage currents at SPICE level guarantees the most accurate results, however not feasible means in high complexity ICs. This performs adversely for Monte-Carlo iterations for statistical analysis. In this paper we introduced an accurate machine learning technique to model statistical and operating variation aware estimation from Artificial Neural Network and regression based Multivariate Polynomial Regression which exhibits innately faster computation and attained error less than 1% for the targeted 16nm FinFET technology node although model is black box for any technology. The accuracy of the proposed technique has been tested over several basic cells and estimation of the complex circuits have been carried out utilizing the pre-modelled basic cells.

Abstract

India graduates 1.5 million engineering students every year, majority of them from its Tier 2 and Tier 3 colleges where there is severe shortage of qualified faculty and lab infrastructure, and where English is second or third language for most students. To provide affordable virtual laboratories to these engineering colleges, Government of India runs the Virtual Labs project with a select set of participating institutions to create virtual labs required for entire engineering student population of India. The program suffers from two problems: 1) lack of focus on pedagogy and learnability of labs being created, and 2) little ability to scale to more teachers and subject matter experts to produce labs aligned to local contexts. This paper presents a model (LEAD model) for the design of virtual labs for a data structures and algorithms course in computer science and is intended to address the problems stated above. The model …

Abstract

Higher yield, climbing transistor counts and shrinking dimensions of a single Integrated Circuit (IC) have always been the demands in the fabrication market. However, this increased complexity and miniaturization of transistors present a challenge, due to high critical process variations combined with a ubiquitous presence of temperature and supply voltage variations, to achieve the required specification bounds on the desired performance of the circuits. Since optimization has become a very crucial task in IC design, the paper presents an efficient transistor sizing based optimization technique of the CMOS circuits to achieve low power, high performance and high yield design goals. The proposed memetic algorithm judiciously utilizes a threshold based local search procedure to improve convergence in its inherent genetic nature. The algorithm optimizes with the effect of temperature ሾെ૞૞ܗܜ૞૛૚ሿԨ and supply voltage േ૚૙Ψ variations and in addition a number of statistically sampled sets generated as Gaussian, Latin Hypercube and Correlation Screened schemes of process variations. The proposed technique is applicable to any technology node and has been tested over several standard single-stage and some complex multi-stage digital circuits designed using a Multi-Gate high-K dielectric (MGK) 22nm CMOS model. The reduction in leakage power with propagation delay goes as high as ૞૜Ψ with ૢΨ respectively, as observed across the various digital circuits

Abstract

The formidable increase in the number of smaller and smarter embedded devices has compelled programmers to develop more and more specialized application programs for these systems. These resource intensive programs that have to be executed on limited memory systems make a strong case for compiler optimizations that reduce the executable size of programs. Standard compilers (like LLVM) offer an out-of-the-box -Oz optimization option—just a series of compiler optimization passes—that is specifically targeted for the reduction of the generated executable size. In this paper, we aim to analyze the effects of optimizations of LLVM compiler on the reduction of executable size. Specifically, we take the size of the executable as a metric and attempt to divide the -Oz series into logical groups and study their individual effects; while also study the effect of their combinations. Our preliminary study over SPEC CPU 2017 benchmarks gives us an insight into the comparative effect of the groups of passes on the executable size. Our work has potential to enable the user to tailor a custom series of passes so as to obtain the desired executable size

Abstract

Polar codes have a very good error correcting capacity compared to turbo and LDPC codes of similar length. They are the first to attain the channel capacity. The aim of the proposed work is to design an Area and Power optimal 2b SC polar decoder exhibiting reduced area and power without degrading the latency by iterative decomposition technique. The targeted performances in decoder architecture are achieved by novel reformulation of F-node, G-node and P-nodes.

Abstract

Sparse neural networks are efficient in both memory and compute when compared to dense neural networks. But on parallel hardware such as GPU, sparse neural networks result in small or no runtime performance gains. On the other hand, structured sparsity patterns like filter, channel and block sparsity result in large performance gains due to regularity induced by structure. Among structured sparsities, block sparsity is a generic structured sparsity pattern with filter and channel sparsity being sub cases of block sparsity. In this work, we focus on block sparsity and generate efficient block sparse convolutional neural networks using our approach DBSR (Dynamic block sparse reparameterization). Our DBSR approach, when applied on image classification task over Imagenet dataset, decreases parameters and FLOPS of ResneXt50 by a factor of 2x with only increase of 0.48 in Top-1 error. And when extended to the task of semantic segmentation, our approach reduces parameters and FLOPS by 30% and 20% respectively with only 1% decrease in mIoU for ERFNet over Cityscapes dataset