Abstract

In this paper, we propose a fully parallel and pipelined architecture for stereo vision on FPGAs using Semi-Global Matching with Census Transform being used underneath. Further, we extend the above streaming architecture so that multiple pixels can be processed in a data parallel fashion. We expose this data parallelism through dependency relaxation. This establishes a trade-off between accuracy and throughput of the hardware. We tested the proposed architecture on Virtex-7 FPGA using KITTI 2012 and KITTI 2015 datasets. On images of resolution 1280x960, with 64 disparity levels, we are able to run our hardware design at 100 MHz. At this frequency, our design is able to process 322 frames per second which is 1.6 times faster than the state-of-the-art SGM implementation on FPGA. Our system can be scaled to a higher resolution image.

Abstract

Load identification is an essential step in Non-Intrusive Load Monitoring (NILM), a process of estimating the power consumption of individual appliances using only whole-house aggregate consumption. Such estimates can help consumers and utility companies improve load management and save power. Current state-of-the-art methods for load identification generally use either steady state or transient features for load identification. We hypothesize that these are complementary features and so a hybrid combination of them will result in an improved appliance signature. We propose a novel hybrid combination that has the advantage of being low-dimensional and can thus be easily integrated with existing classification models to improve load identification. Our improved hybrid features are then used for building appliance identification models using Naive Bayes, KNN, Decision Tree and Random Forest classifiers. The proposed NILM methodology is evaluated for robustness in changing environments. An automated data collection setup is established to capture 7 home appliances aggregate data under varying voltages. Experimental results show that our proposed feature fusion based algorithms are more robust and outperform steady state and transient feature-based algorithms by at least +9% and +15% respectively.

Abstract

Images when processed using various enhancement techniques often lead to edge degradation and other unwanted artifacts such as halos. These artifacts pose a major problem for photographic applications where they can denude the quality of an image. There is a plethora of edge-aware techniques proposed in the field of image processing. However, these require the application of complex optimization or post-processing methods. Local Laplacian Filtering is an edge-aware image processing technique that involves the construction of simple Gaussian and Laplacian pyramids. This technique can be successfully applied for detail smoothing, detail enhancement, tone mapping and inverse tone mapping of an image while keeping it artifact-free. The problem though with this approach is that it is computationally expensive. Hence, parallelization schemes using multi-core CPUs and GPUs have been proposed. As is well known, they are not power-efficient, and a well-designed hardware architecture on an FPGA can do better on the performance per watt metric. In this paper, we propose a hardware accelerator, which exploits fully the available parallelism in the Local Laplacian Filtering algorithm, while minimizing the utilization of on-chip FPGA resources. On Virtex-7 FPGA, we obtain a 7.5x speed-up to process a 1 MB image when compared to an optimized baseline CPU implementation. To the best of our knowledge, we are not aware of any other hardware accelerators proposed in the research literature for the Local Laplacian Filtering problem.

Abstract

In this paper, the role of the shape of gold nanoparticles in improving the efficiency of sensing of biomolecules using Radio Frequency (RF) has been studied. The analysis has been performed with the help of an Interdigitated Capacitor (IDC) based structure using the CAD tool, High Frequency Structure Simulator (HFSS). The frequency response and E-Field distribution of various shapes of gold nanoparticles have been analysed. The results indicate that the detection efficiency of RF sensing of biomolecules improves significantly in the presence of gold nanoparticles. The shape, as well as the position of biomolecules around the gold nanoparticles, affects the efficiency of detection. These results open up new avenues for developing highly efficient nanoparticle-Radiofrequency-based sensors.

Abstract

Pulse Arrival Time (PAT) derived from Electrocardiogram (ECG) and Photoplethysmogram (PPG) for cuff-less Blood Pressure (BP) measurement has been a contemporary and widely accepted technique. However, the features extracted for it are conventionally from an isolated pulse of ECG and PPG signals. As a result, the estimated BP is intermittent. Objective: This paper presents feature extraction from each beat of ECG and PPG signals to make BP measurements uninterrupted. These features are extracted by employing Haar transformation to adaptively attenuate measurement noise and improve the fiducial point detection precision. Method: the use of only PAT feature as an independent variable leads to an inaccurate estimation of either Systolic Blood Pressure (SBP) or Diastolic Blood Pressure (DBP) or both. We propose the extraction of supplementary features that are highly correlated to physiological parameters. Concurrent data was collected as per the Association for the Advancement of Medical Instrumentation (AAMI) guidelines from 171 human subjects belonging to diverse age groups. An Adaptive Window Wavelet Transformation (AWWT) technique based on Haar wavelet transformation has been introduced to segregate pulses. Further, an algorithm based on log-linear regression analysis is developed to process extracted features from each beat to calculate BP. Results: The mean error of 0.43 and 0.20 mmHg, mean absolute error of 4.6 and 2.3 mmHg, and Standard deviation of 6.13 and 3.06 mmHg is achieved for SBP and DBP respectively. Conclusions: The features extracted are highly precise and evaluated BP values are as per the AAMI standards. Clinical Impact: This continuous real-time BP monitoring technique can be useful in the treatment of hypertensive and potential-hypertensive subjects.

Abstract

This brief presents a CMOS-only ultra low power voltage reference of 0.925V which is designed and simulated in TSMC 180nm technology. Current mixing between SelfBiased Self Cascode MOSFET (SBSCM) and Self Cascode MOSFET (SCM) pair is introduced along with stacking of proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltage generators to get second order curvature compensation. Temperature coefficient (TC) of 3.75ppm/°C over a wide temperature range of -55°C to 140°C is achieved. To feed on the power reduction requirement of low power biomedical applications, the entire circuit is designed in sub-threshold region. Therefore, the total power consumption is 27nW @ 1.45V at room temperature (27°C). Furthermore, a supply independent current bias aids in realizing high PSRR of -91dB @ 10Hz / -50dB @ 100MHz and line regulation of 0.0779%/V over a supply range 1.45V to 3.6V. Besides, an employed trimming technique attenuates the process spread from ±3% to ±0.3%. Moreover, the proposed design occupies an active area of 0.0054mm 2 only.

Abstract

This brief presents a novel PVT-invariant CMOS relaxation oscillator for Real-Time Clock (RTC) applications. The proposed design is compatible to work in a low supply voltage domain of SoC. The PVT invariance is achieved by a unique circuit implementation of introducing a self-adaptive mechanism that dynamically modifies the time constant of the oscillator core. Moreover, the design is accompanied by a digital calibration unit for further process compensation. Besides, the introduced supply independent bias circuit has greatly improved the supply regulation of the oscillator frequency. In addition, the design utilizes a complementary to absolute temperature (CTAT) current for temperature compensation. Area efficiency is enhanced by replacing bigger passive device i.e, resistor with an adaptive MOS resistor. The obtained results show that the minimum temperature coefficient (TC) of 31.236ppm/°C is achieved over a range of -40°C to 100°C. The resultant phase noise of -140dBc/Hz@1MHz is observed. The design has achieved a good power efficiency of 1.65nW/KHz at room temperature without a calibration unit. The line sensitivity (LS) of 0.1159%/V is noted in the range of 0.7V to 1.2V. Nevertheless, the entire system occupies an active area of 0.0509mm^2 with a power consumption of 90nW@0.7V. Also, the leakage current of the complete system is <; 54pA. Therefore, the proposed design aims at providing a production-friendly, ease of integration and low-cost solution.

Abstract

he paper presents an eight transistor (8T) pico-watt current reference with a novel method of rectifying the prob-lem of exponential power increase w.r.t temperature in traditionalsub-nW references. The proposed current reference is obtainedby modifying the traditional beta-multiplier architecture to scale-down the power consumption without sacrificing area. Theconstancy of power consumption w.r.t temperature is achievedby exploiting the voltage-current characteristics of a leakagetransistor in the modified architecture. The proposed currentreference, implemented in UMC 55nm technology, occupies anarea of0.00035mm2. It is designed for a current of 60pA andachieves an accuracy of19ppm/0Cover a wide temperaturerange of−550Cto1250C. The reported line sensitivity for thecurrent reference is 0.07%/V in the supply range of 1.2V - 4V.Post-trim results show a constant power consumption of 144pWw.r.t temperature and process variations @1.2V supply.

Abstract

This paper presents a robust short-term electrical load forecasting framework that can capture variations in building operation, regardless of building type and location. Nine different hybrids of recurrent neural networks and clustering are explored. The test cases involve five commercial buildings of five different building types, i.e., academic, research laboratory, office, school and grocery store, located at five different locations in Bangkok-Thailand, Hyderabad-India, Virginia-USA, New York-USA, and Massachusetts-USA. Load forecasting results indicate that the deep learning algorithms implemented in this paper deliver 20–45% improvement in load forecasting performance as compared to the current state-of-the-art results for both hour-ahead and 24-ahead load forecasting. With respect to sensitivity analysis, it is found that: (i) the use of hybrid deep learning algorithms can take as less as one month of data to …

Abstract

In this paper, we propose an accurate and computationally efficient Gradient Boosting approach for the estimation of statistical variations aware leakage power and propagation delay in the CMOS/FinFET standard digital cells. The proposed model estimates the leakage power and propagation delay w.r.t variations in process, temperature (−55°C to 125°C) and supply voltage(±10% variations). The distinguishing feature of the proposed approach is its compatibility with both CMOS and FinFET technologies. Moreover, the performance of the proposed model is consistent with various technology nodes. Exhaustive tests report an average error of <1% in 16nm CMOS and FinFET standard digital cells w.r.t analog HSPICE simulations with several orders increase in computational speed. Further, the complex cell estimation can be carried out through precharacterized standard cells abstaining longer simulations.