Abstract

This paper presents a low-dropout regulator (LDO)
designed and implemented in TSMC 180 nm CMOS process,
incorporating a curvature-compensated band-gap reference for
precision voltage regulation. The LDO delivers a stable 1.8V
output from 2-3.3V supply while operating reliably across PVT
variations from-55°C to 170°C. The design achieves a quiescent
current of 35 µA and supports a maximum load current of 20mA
with 99.9% current efficiency and 70 µW power consumption.
The results demonstrate a DC PSRR of-81dB, a phase margin
of 65°under full load, and a startup time of 1.79 µs. Monte
Carlo analysis reveals that Vref has a standard deviation of 0.87
mV, and the worst-case temperature coefficient across process
corners is 27 ppm°/C. This architecture is suitable for low power
and wide temperature range based applications.
Keywords--Low-dropout regulator (LDO), bandgap refer
ence (BGR), curvature compensation, Power Supply Rejection
Ratio(PSRR), Process Voltage Temperature (PVT) variations,
Proportional To Absolute Temperature(PTAT), Complementary
To Absolute Temperature(CTAT)

Abstract

FinFET technology has emerged as a solution to
mitigate the short-channel effects in CMOS technology. However, with continued technology scaling, leakage power is now emerging as a primary contributor to total power consumption. Additionally, aging effects, compounded by process, voltage, and temperature (PVT) variations, significantly degrade leakage behavior over time, resulting in high data variance and
posing challenges for conventional machine learning models to generalize aging-induced leakage trends. This paper proposes a physics-informed machine learning architecture based on a deaggregation-based methodology that effectively captures the complex, non-linear relationship between aging and leakage
power across PVT, incorporating both NBTI and HCI effects, by leveraging pattern-oriented knowledge. Experimental evaluations on 7nm and 10nm high-performance FinFET standard cells demonstrate mean absolute percentage error (MAPE) improvements of 52.71% and 54.44%, respectively, compared to stateof-the-art standalone boosting and deep learning models. The proposed method presents a robust and omputationally efficient alternative to traditional simulation-based approaches for agingaware power estimation in digital circuit design.

Abstract

This paper presents the design and analysis of
a fast-transient buck converter employing a low-complexity, ripple-based constant on-time (R-COT) control architecture. To overcome stability limitations in conventional R-COT systems, a ripple synthesizer is proposed that combines inductor current ripple with DC output voltage feedback, ensuring robust
regulation across varying load conditions. A digitally assisted calibration technique for the zero-current detection comparator mitigates both static offset and dynamic delay, enabling precise Zero Current Sense (ZCS) detection under Discontinuous Mode
(DCM) operation. Additionally, a valley current sensing scheme is introduced to estimate average load current via ripple midpoint sampling, supporting load adaptive control. These enhancements improve load regulation and transient performance without added system complexity. The implemented converter achieves
a transient undershoot of ±30mV and load regulation within 10 mV across a 0 − 10 A range, making it well suited for highperformance PMIC applications such as memory and processor power delivery.

Abstract

The contribution of leakage power to total power
consumption increases as the technology node continues to scale, making the design of energy-efficient digital circuits challenging. Traditional ML models provide only point estimates of test data and do not directly output the variability introduced by physical and environmental fluctuations. In this paper, we explore the application of probabilistic modeling techniques, such as Natural Gradient Boosting (NGBoost), to quantify leakage power distributions rather than point estimates, thereby capturing the
uncertainty caused by PVT variations. The distinguishing feature of the current approach is the use of MAPIE (Model Agnostic Prediction Interval Estimator), which provides prediction intervals using conformal predictive distributions and leverages
gradient boosting algorithms for fast and accurate predictions. We evaluated the scalability of the approach in 7nm and 10nm standard cell libraries comprising 13 logic gates, reporting an average MAPE (Mean Absolute Percentage Error) of 1.6768%
and 1.6764%, respectively, using MAPIE in combination with CatBoostRegressor. The method also highlights low-confidence regions, enabling targeted improvements that enhance the robustness of leakage power estimations in digital circuits.

Abstract

Rapid detection of creatinine level is significant for the diagnosis of renal dysfunction. Conventional methods used for creatinine detection are not portable and cannot provide real-time results. This paper describes the design and validation of a microwave biosensor to overcome these limitations. The resonator is designed using a complementary split-ring resonator (CSRR) and an interdigitated capacitor (IDC) fabricated on a FR-4 substrate of dimensions 50×25mm2. Simulations showed a resonance frequency of 2.013 GHz, while measurement results yielded a resonance of 1.941 GHz, with a deviation of 72 MHz. The fabricated device was tested with 10μL creatinine samples of 0.8 to 2.0mg/dL, which are in the physiological range. A sensitivity of 0.77% is achieved for detecting changes in concentration in chemical solutions. These results show the capability of the biosensor for real-time biomedical diagnosis.

Abstract

In this paper, we propose an efficient and robust framework for estimating leakage power while considering statistical variations in process parameters, supply voltage, and temperature (PVT) in FinFET-based digital circuits. Extensive testing reports an average error of less than 1 % in the ML models for standard digital cells, with an average MAPE (Mean Absolute Percentage Error) of 0.764%,0.770%, and 0.814% in the 7 nm,10 nm, and 16 nm FinFET technology nodes, respectively, which ensures a highly accurate leakage estimate for larger circuits. Additionally, we investigated the transistor-level approach, which distinctively estimates subthreshold, gate, and body leakage power using only transistor-level models and stacks, and investigated its trade-offs to gate-level models. Using ML techniques, we achieve a speedup of over 400 times compared to HSPICE for the characterization of digital blocks, using which complex cell designs can be analyzed across various input test combinations, significantly saving the time required for extensive simulations.

Abstract

A 16-Gb/s continuous-time linear equalizer (CTLE) is designed in 28-nm CMOS technology, featuring an active inductor load and feedforward compensation to enhance high-frequency performance. The proposed design features a power-efficient architecture, achieving a remarkable eye opening of 45.75 ps and a vertical differential eye opening of 781.19 mV. The design achieves reliable operation for channel losses of 9 dB, consuming a total power of 3.3 mW from a 0.9 V supply. This CTLE provides an energy-efficient solution for high-speed SerDes applications, with a calculated figure-of-merit of 0.022 pJ/hit/dB.

Abstract

FinFET, now firmly established in leading VLSI industries for their superior performance, exhibit heightened aging susceptibility that poses significant reliability challenges. The aggressive scaling of technology nodes has further compromised circuit reliability in recent years, highlighting the need for effective aging mitigation techniques. Recent advancements in the miniaturization of nanoscale technology have demonstrated the potential of optimizing performance parameters in standard cells using machine learning models and optimization algorithms through device sizing modifications. Building on this progress, we propose a methodology for optimizing performance parameters in 16nm high-performance (HP) FinFET for the first time. The approach leverages a multi-objective optimization algorithm framework to mitigate aging impacts across PVT variations while addressing NBTI and HCI effects by optimally adjusting FinFET design parameters, including channel length (lg), width (tfin), and height (hfin). With SPICE simulations, time-series datasets were generated to train machine learning models that achieved an R² score exceeding 0.99 and a mean absolute percentage error below 1% across standard cells. Our approach yields a significant simulation speedup and a reduction in simulation workload compared to traditional SPICE simulations. Using the proposed optimization algorithm framework, we improved the power-delay product (PDP) by up to 36.97% under non-aging conditions and 34.94% with aging considered with respect to the nominal dimension at the fresh year, demonstrating significant performance gains for FinFET-based standard cells. The experimental results on 12 distinct complex cells validate the aging mitigation across years.

Abstract

Globesity has widely affected the world population. It is a multifactorial health problem. Obesity can be caused by high-fat intake, high-calorie intake, physical inactivity, age, gender, or hormonal issues that can induce many health issues, such as cardiovascular disorders, diabetes, and metabolic disorders. Health facilities are insufficient to provide services to the whole population. In such a case, introducing Artificial Intelligence (AI) in the health sector is one of the most significant steps that can be taken. With the help of AI, the prognosis, diagnosis, and treatment can be provided to individuals within their homes and setups without any physical interactions. Assembling the data collected with AI can help to give more information on the type of obesity prevailing in a particular society so that it could be prevented in the population. Since AI learning is relatively novel within the existing system of medicine, enabling …

Abstract

A method for describing, distributing and re-producing specifications of analog IC using AI models, is fulfilled in the ongoing description by (a) creating an AI model to represent the electrical specifications of the analog integrated circuit over a specified range of PVT, input and output loading, and aging conditions,(b) training the AI model with simulation data associated with the analog IC, wherein the simulation inputs include a plurality of instances of PVT (Process, Voltage, Temperature), input/output loading, and aging conditions,(c) electronically enabling peripheral functions with the AI model into an AI model pack, wherein the peripheral functions include a set of computer code modules to extract the AI model, perform user requested operations, calculate specifications of the analog IC on-the-fly and interact with the user, and (d) distributing the encrypted AI model pack to a plurality of users.