Abstract

This paper presents an ultra-low-power CMOS
voltage reference (VR) design that achieves very low line sen-
sitivity and a wide temperature range of operation. The core
architecture consists of only four transistors and employs a dual
regulation loop topology to enhance the line sensitivity. A gate-
source shorted PMOS serves as the main current source of
the core. An additional proportional to absolute temperature
(PTAT) generator connected to the body of the PMOS current
source to modulate Vth at subzero temperatures while bulk
diode leakage control is utilized to ensure reliable operation at
higher temperature. Simulated in a 0.18 μm CMOS process, the
proposed VR delivers a reference voltage of 451.6 mV while
consuming only 37.6 pW power. It has a line sensitivity (LS) of
0.009%/V and operates over a temperature range from -30°C to
160°C with temperature coefficient (TC) of 70.2 ppm/◦C.

Abstract

This paper presents a jitter-peaking-free, referenceless digital clock and data recovery (D-CDR) circuit implemented in a dual-loop D/PLL CDR architecture with multi-bit decimation. The design combines a DLL-based VCDL loop to suppress high-frequency jitter components, combined with a PLL-based
VCO loop for stabilizing low-frequency jitter, resulting in a
flat jitter transfer function. A multi-bit decimator losslessly
downsamples phase detector outputs, significantly reducing quantization noise and minimizing recovered clock jitter. The dualloop structure enhances loop dynamics, achieving high jitter tolerance (JTOL = 0.20 UI) and low jitter transfer (JTRAN)
without peaking with a corner frequency of 12 MHz, simulated
JTRAN BW is 7MHz. These features make the proposed D-CDR
highly suitable for high-speed serial and optical link applications.

Abstract

Hardware security in energy-constrained systems
requires highly stable primitives. This paper presents a novel weak Physical Unclonable Function (PUF) architecture implemented in a 28-nm CMOS process, leveraging mismatch-induced variations between two compact all-CMOS voltage reference circuits. The PUF response is derived from mismatch-dominated reference voltages, enabling robust entropy extraction while inherently suppressing sensitivity to environmental variations. To ensure reliable low-voltage operation at a 0.9 V nominal supply voltage, the design utilizes ultra-low threshold voltage (ULVT) devices. Simulation results for a 256-bit PUF array show
an average inter-chip uniqueness of 50.47%. Furthermore, the design demonstrates strong native stability, significantly reducing the reliance on error-correction codes and helper data overhead.
It maintains greater than 97% accuracy across a temperature range of −40◦C to 125◦C and supply voltage variations from 0.65 V to 1.1 V. This architecture provides a scalable and practical approach for hardware identification and cryptographic key generation in advanced nodes.

Abstract

This paper presents a low-dropout regulator (LDO)
designed and implemented in TSMC 180 nm CMOS process,
incorporating a curvature-compensated band-gap reference for
precision voltage regulation. The LDO delivers a stable 1.8V
output from 2-3.3V supply while operating reliably across PVT
variations from-55°C to 170°C. The design achieves a quiescent
current of 35 µA and supports a maximum load current of 20mA
with 99.9% current efficiency and 70 µW power consumption.
The results demonstrate a DC PSRR of-81dB, a phase margin
of 65°under full load, and a startup time of 1.79 µs. Monte
Carlo analysis reveals that Vref has a standard deviation of 0.87
mV, and the worst-case temperature coefficient across process
corners is 27 ppm°/C. This architecture is suitable for low power
and wide temperature range based applications.
Keywords--Low-dropout regulator (LDO), bandgap refer
ence (BGR), curvature compensation, Power Supply Rejection
Ratio(PSRR), Process Voltage Temperature (PVT) variations,
Proportional To Absolute Temperature(PTAT), Complementary
To Absolute Temperature(CTAT)

Abstract

FinFET technology has emerged as a solution to
mitigate the short-channel effects in CMOS technology. However, with continued technology scaling, leakage power is now emerging as a primary contributor to total power consumption. Additionally, aging effects, compounded by process, voltage, and temperature (PVT) variations, significantly degrade leakage behavior over time, resulting in high data variance and
posing challenges for conventional machine learning models to generalize aging-induced leakage trends. This paper proposes a physics-informed machine learning architecture based on a deaggregation-based methodology that effectively captures the complex, non-linear relationship between aging and leakage
power across PVT, incorporating both NBTI and HCI effects, by leveraging pattern-oriented knowledge. Experimental evaluations on 7nm and 10nm high-performance FinFET standard cells demonstrate mean absolute percentage error (MAPE) improvements of 52.71% and 54.44%, respectively, compared to stateof-the-art standalone boosting and deep learning models. The proposed method presents a robust and omputationally efficient alternative to traditional simulation-based approaches for agingaware power estimation in digital circuit design.

Abstract

This paper presents the design and analysis of
a fast-transient buck converter employing a low-complexity, ripple-based constant on-time (R-COT) control architecture. To overcome stability limitations in conventional R-COT systems, a ripple synthesizer is proposed that combines inductor current ripple with DC output voltage feedback, ensuring robust
regulation across varying load conditions. A digitally assisted calibration technique for the zero-current detection comparator mitigates both static offset and dynamic delay, enabling precise Zero Current Sense (ZCS) detection under Discontinuous Mode
(DCM) operation. Additionally, a valley current sensing scheme is introduced to estimate average load current via ripple midpoint sampling, supporting load adaptive control. These enhancements improve load regulation and transient performance without added system complexity. The implemented converter achieves
a transient undershoot of ±30mV and load regulation within 10 mV across a 0 − 10 A range, making it well suited for highperformance PMIC applications such as memory and processor power delivery.

Abstract

The contribution of leakage power to total power
consumption increases as the technology node continues to scale, making the design of energy-efficient digital circuits challenging. Traditional ML models provide only point estimates of test data and do not directly output the variability introduced by physical and environmental fluctuations. In this paper, we explore the application of probabilistic modeling techniques, such as Natural Gradient Boosting (NGBoost), to quantify leakage power distributions rather than point estimates, thereby capturing the
uncertainty caused by PVT variations. The distinguishing feature of the current approach is the use of MAPIE (Model Agnostic Prediction Interval Estimator), which provides prediction intervals using conformal predictive distributions and leverages
gradient boosting algorithms for fast and accurate predictions. We evaluated the scalability of the approach in 7nm and 10nm standard cell libraries comprising 13 logic gates, reporting an average MAPE (Mean Absolute Percentage Error) of 1.6768%
and 1.6764%, respectively, using MAPIE in combination with CatBoostRegressor. The method also highlights low-confidence regions, enabling targeted improvements that enhance the robustness of leakage power estimations in digital circuits.

Abstract

Rapid detection of creatinine level is significant for the diagnosis of renal dysfunction. Conventional methods used for creatinine detection are not portable and cannot provide real-time results. This paper describes the design and validation of a microwave biosensor to overcome these limitations. The resonator is designed using a complementary split-ring resonator (CSRR) and an interdigitated capacitor (IDC) fabricated on a FR-4 substrate of dimensions 50×25mm2. Simulations showed a resonance frequency of 2.013 GHz, while measurement results yielded a resonance of 1.941 GHz, with a deviation of 72 MHz. The fabricated device was tested with 10μL creatinine samples of 0.8 to 2.0mg/dL, which are in the physiological range. A sensitivity of 0.77% is achieved for detecting changes in concentration in chemical solutions. These results show the capability of the biosensor for real-time biomedical diagnosis.

Abstract

In this paper, we propose an efficient and robust framework for estimating leakage power while considering statistical variations in process parameters, supply voltage, and temperature (PVT) in FinFET-based digital circuits. Extensive testing reports an average error of less than 1 % in the ML models for standard digital cells, with an average MAPE (Mean Absolute Percentage Error) of 0.764%,0.770%, and 0.814% in the 7 nm,10 nm, and 16 nm FinFET technology nodes, respectively, which ensures a highly accurate leakage estimate for larger circuits. Additionally, we investigated the transistor-level approach, which distinctively estimates subthreshold, gate, and body leakage power using only transistor-level models and stacks, and investigated its trade-offs to gate-level models. Using ML techniques, we achieve a speedup of over 400 times compared to HSPICE for the characterization of digital blocks, using which complex cell designs can be analyzed across various input test combinations, significantly saving the time required for extensive simulations.

Abstract

A 16-Gb/s continuous-time linear equalizer (CTLE) is designed in 28-nm CMOS technology, featuring an active inductor load and feedforward compensation to enhance high-frequency performance. The proposed design features a power-efficient architecture, achieving a remarkable eye opening of 45.75 ps and a vertical differential eye opening of 781.19 mV. The design achieves reliable operation for channel losses of 9 dB, consuming a total power of 3.3 mW from a 0.9 V supply. This CTLE provides an energy-efficient solution for high-speed SerDes applications, with a calculated figure-of-merit of 0.022 pJ/hit/dB.