Abstract

Traditional chemical analysis techniques require high operational costs and sophisticated equipment and cannot provide real-time monitoring. However, it can be achieved with less expensive and simpler equipment by using alternative sensing technologies, such as Radio Frequency (RF) sensing and capacitive sensing, which overcome these limitations. However, RF-based sensing of heterogeneous liquid mixtures remains challenging due to their complex effective permittivity. This article introduces a low-cost, highly sensitive RF biosensor based on a nested complementary multiple split-ring resonator (CSRR) enabling the detection of concentration variations in multi-solute mixtures such as ethanol, sodium chloride, and L-lysine. The sensor was fabricated with dimensions of 38.8 × 22.8 mm2 with high fabrication yield. The sensor operates at a measured resonant frequency of 2.56 GHz. The sensor performance is stabilized using a polylactic acid (PLA) wall and Whatman paper to ensure uniform sample distribution over the sensing region. A normalized sensitivity of 0.637% is achieved, representing an improvement over a single-ring CSRR architecture.

Abstract

Radio frequency (RF) sensing is a fast and efficient technique for biomolecule detection using small sample volumes. Interdigitated capacitor (IDC) sensors are widely used in biosensing due to their compactness, ease of fabrication, and high quality factor. However, the design of the IDC sensor and the frequency tuning range (FTR) of the Vector Network Analyzer (VNA) are interdependent and must be considered jointly. In this work, we present a methodology to determine optimal IDC dimensions for detecting biomolecules based on dielectric constants for a given VNA, or conversely, to identify the required VNA frequency range for a given IDC-based biosensor. For breast cancer cell detection, the lowest calculated frequency range was 644.2-859.5 MHz (FTR: 28.64%), while the minimum FTR of 22.09% occurred at 4.23-5.28 GHz. Theoretically obtained results are compared with Ansys HFSS simulations and the impact of various IDC parameters on resonant frequency is analyzed.

Abstract

This paper presents a picowatt, process and
temperature-compensated voltage reference for energy-harvested IoT nodes, producing a 0.36 V output. The design eliminates trimming, startup circuit, and on-chip resistor, minimizing complexity and area. A non-loading voltage-divider enables accurate reference generation at supply voltages down to 0.5 V, ensuring robust operation under deeply scaled supplies. Furthermore, a PMOS source-follower is repurposed as a voltage summer,
simplifying the architecture, reducing the active device count, and lowering power consumption. Process compensation is achieved through a device-level technique that limits output variation to a σ/µ of 0.39%, while a native-VTH transistor (NVT) improves line sensitivity. Implemented in 180-nm CMOS technology, the
circuit achieves a nominal temperature coefficient of 36.5 ppm/◦ C and exhibits a typical line sensitivity of 0.14%/V over a supply range of 0.5-2 V. Additionally, the circuit consumes only 72 pW at a 0.5 V supply and occupies an active area of 0.0054 mm2.

Abstract

This paper presents a sub-nW relaxation oscillator
without using large resistors to achieve low area, thereby making
it suitable for IoT applications. Gate-leakage-based voltage and
current references have been used to achieve an effective resis-
tance of Vref /Iref , thereby scaling down the power consumption
to the pW level while consuming low area. The oscillator is
designed in 65 nm process and occupies an area of 0.007 mm2.
It generates a clock of 28 Hz and post-layout simulations show
a temperature coefficient (TC) of 56 ppm/◦C in the temperature
range of −55◦C to 80◦C. It exhibits a line sensitivity of 1.83%/V
in the supply range of 1.2 V to 2.5 V and consumes 445 pW
power at 1.2 V supply. The power efficiency is observed to be
15.9 pW/Hz.

Abstract

This paper presents a low-voltage, low-swing, single
transistor current mirror implemented in Fully Depleted Silicon
on-Insulator (FD-SOI) technology. By leveraging body-effect
feedback through the back gate, the proposed current mir
ror mitigates channel-length modulation, achieving high output
resistance and reduced drain-voltage sensitivity with minimal
headroom (one overdrive voltage VOV). The approach requires
no additional amplifiers, thereby minimizing power consump
tion and design complexity. Implemented in GF-22nm FD-SOI,
the proposed current mirror demonstrates a 10× increase in
output impedance under nominal conditions and maintains a
6× improvement across the temperature range of −20◦C to
100◦C, without requiring any compensation circuitry. A 5-T OTA
is used as a demonstration vehicle to validate the technique.
Compared with a conventional current mirror operating under
similar headroom conditions, the proposed design achieves up to
20dB improvement in CMRR, with negligible power and area
overhead.

Abstract

Accurate transistor sizing remains a major challenge
in analog integrated circuit design due to the highly nonlinear and
many-to-one relationship between device dimensions and circuit
performance metrics. Conventional design flows rely on repeated
SPICE simulations and manual tuning, resulting in significant
computational cost and long design cycles. A feasibility-aware
inverse machine framework is proposed for specification-driven
analog circuit design. The framework directly determines tran
sistor dimensions from target performance specifications such
as gain, bandwidth, phase margin, and power. A multi-output
surrogate model enables rapid performance prediction, while a
genetic-algorithm-based inverse optimizer searches for feasible
sizing solutions. The framework introduces specification-space
feasibility filtering prior to optimization to prevent convergence
toward unattainable targets. Experimental results across mul
tiple analog circuit architectures demonstrate that the proposed
method produces SPICE-validated transistor sizing solutions with
specification errors below 5%.

Abstract

This paper presents an ultra-low-power CMOS
voltage reference (VR) design that achieves very low line sen-
sitivity and a wide temperature range of operation. The core
architecture consists of only four transistors and employs a dual
regulation loop topology to enhance the line sensitivity. A gate-
source shorted PMOS serves as the main current source of
the core. An additional proportional to absolute temperature
(PTAT) generator connected to the body of the PMOS current
source to modulate Vth at subzero temperatures while bulk
diode leakage control is utilized to ensure reliable operation at
higher temperature. Simulated in a 0.18 μm CMOS process, the
proposed VR delivers a reference voltage of 451.6 mV while
consuming only 37.6 pW power. It has a line sensitivity (LS) of
0.009%/V and operates over a temperature range from -30°C to
160°C with temperature coefficient (TC) of 70.2 ppm/◦C.

Abstract

This paper presents a jitter-peaking-free, referenceless digital clock and data recovery (D-CDR) circuit implemented in a dual-loop D/PLL CDR architecture with multi-bit decimation. The design combines a DLL-based VCDL loop to suppress high-frequency jitter components, combined with a PLL-based
VCO loop for stabilizing low-frequency jitter, resulting in a
flat jitter transfer function. A multi-bit decimator losslessly
downsamples phase detector outputs, significantly reducing quantization noise and minimizing recovered clock jitter. The dualloop structure enhances loop dynamics, achieving high jitter tolerance (JTOL = 0.20 UI) and low jitter transfer (JTRAN)
without peaking with a corner frequency of 12 MHz, simulated
JTRAN BW is 7MHz. These features make the proposed D-CDR
highly suitable for high-speed serial and optical link applications.

Abstract

Hardware security in energy-constrained systems
requires highly stable primitives. This paper presents a novel weak Physical Unclonable Function (PUF) architecture implemented in a 28-nm CMOS process, leveraging mismatch-induced variations between two compact all-CMOS voltage reference circuits. The PUF response is derived from mismatch-dominated reference voltages, enabling robust entropy extraction while inherently suppressing sensitivity to environmental variations. To ensure reliable low-voltage operation at a 0.9 V nominal supply voltage, the design utilizes ultra-low threshold voltage (ULVT) devices. Simulation results for a 256-bit PUF array show
an average inter-chip uniqueness of 50.47%. Furthermore, the design demonstrates strong native stability, significantly reducing the reliance on error-correction codes and helper data overhead.
It maintains greater than 97% accuracy across a temperature range of −40◦C to 125◦C and supply voltage variations from 0.65 V to 1.1 V. This architecture provides a scalable and practical approach for hardware identification and cryptographic key generation in advanced nodes.

Abstract

This paper presents a low-dropout regulator (LDO)
designed and implemented in TSMC 180 nm CMOS process,
incorporating a curvature-compensated band-gap reference for
precision voltage regulation. The LDO delivers a stable 1.8V
output from 2-3.3V supply while operating reliably across PVT
variations from-55°C to 170°C. The design achieves a quiescent
current of 35 µA and supports a maximum load current of 20mA
with 99.9% current efficiency and 70 µW power consumption.
The results demonstrate a DC PSRR of-81dB, a phase margin
of 65°under full load, and a startup time of 1.79 µs. Monte
Carlo analysis reveals that Vref has a standard deviation of 0.87
mV, and the worst-case temperature coefficient across process
corners is 27 ppm°/C. This architecture is suitable for low power
and wide temperature range based applications.
Keywords--Low-dropout regulator (LDO), bandgap refer
ence (BGR), curvature compensation, Power Supply Rejection
Ratio(PSRR), Process Voltage Temperature (PVT) variations,
Proportional To Absolute Temperature(PTAT), Complementary
To Absolute Temperature(CTAT)