Abstract
Reservoir Computing (RC) has gained increasing
attention for its efficiency and adaptability in processing time-series and other complex temporal data. While software simulations can easily support large reservoirs by mapping inputs into high-dimensional spaces, hardware implementations remain challenging due to architectural complexity. Most RC systems adopt sequential structures, which simplify hardware but sacrifice the low latency and inherent fault tolerance of parallel architectures. Although innovative memory nonlinearity trade-off mechanisms have been proposed, their integration into hardware has not yet been fully realized. In addition, the widely used hyperbolic tangent activation function is computationally expensive, whereas simplified variants like the Tanh-Linear function lack sufficient nonlinearity, resulting in reduced accuracy. This work presents a fully parallel hardware implementation of the Simple Cycle Reservoir with a novel activation function. A genetic algorithm is integrated and automated to tune the memory nonlinearity trade-off factor, leakage rate, and several other hyperparameters, enabling seamless deployment into hardware. Our unified hardware-software co-optimization framework provides a low- power and high throughput fully parallel reservoir implementation with excellent accuracy. Experiments on standard bench-
mark time-series datasets demonstrate up to a tenfold reduction in prediction error, a 10-100 times improvement in speed, a power-delay product below 0.02 W·μs, and LUT utility to 2% of conventional reservoir implementation with minimal effect on DSP utility.