Abstract
Ever since the induction of Integrated circuits into mainstream usage, numerous research efforts have been made into optimizing the circuits implemented on silicon with respect to Power, Area, Time (PAT), and most recently reliability. Due to the recent insurgence of mobile devices, low power design techniques are being given more emphasis. Power dissipated can be reduced at the device, circuit, system architecture, or software design levels. The focus of this work is aimed towards the reduction of power dissipation in electronic systems, by way of using inexact logic in implementing systems, where error can be tolerated, and/or neglected. An inexact logic circuit is constructed by selectively converting minterms/maxterms of its Boolean function into don’t cares. The intuition in doing this is that by converting only a small fraction of minterms/maxterms into don’t-cares, an inexact version of the Boolean function can be synthesized with a significantly lower area-power-delay footprint than the exact Boolean function. Decision making circuits, which are generally sensitive to errors, have been chosen as the subject of analysis. Several applications are presented where inexactness can be applied, and their performance, in terms of power and system accuracy is quantified with varying levels of inexactness. This thesis also outlines a set of general guidelines to design inexact circuits, on a per case basis. To simplify the process, a heuristic framework to generate inexact circuits with varying levels of inexactness has been implemented. The above mentioned applications are classified into 3 categories based on the impact of the decision made, on system accuracy. These categories are: No impact, Tolerable impact, and Significant impact, on system accuracy. For applications with no impact, the only deciding criteria in introducing inexactness are the overall improvement in power and speed. For applications under the tolerable impact category, a system accuracy parameter should also be considered in validating an inexact circuit. For applications with significant impact, inexactness is seldom tolerated, as system accuracy is critical. Bus coding, Median Filter based Image blurring, and Non-Modular Redundancy (NMR), falling under the no impact, tolerable impact, and significant impact categories respectively share the majority voter as a common decision circuit used. A Least Recently Used (LRU)-variant replacement algorithm for Translation Lookaside Buffers (TLB), and a DCT threshold based image blurring process, with the former having no impact on system accuracy and the latter
having tolerable impact, share a comparator as a decision circuit. Different inexact versions of these decision circuits are generated and their performance parameters with respect to the applications are measured. A comparison has been made with the levels of inexactness and the power dissipation of the system and the system performance. The results obtained promise a drastic reduction in power dissipation, up to 300%, with tolerable deviation in system accuracy. Although critical path delay was not a parameter for optimization, a gain of up to 30% was observed on this front. The chip area and static power dissipation is also reduced significantly. The results obtained validate the use of inexact logic in applications which are either impervious or tolerant to the errors produced due to the inexactness. This provides a new avenue to low power system design, which can be used in congruence to other circuit design, and system level design techniques.