Abstract

This paper presents an ultra-low power CMOS voltage reference (CVR) which is free of amplifier and resistor. A current generator circuit is used to generate a supply independent current to bias the active load in the temperature compensation circuit. Drain-source voltage of two critical MOSFETs is made equal in the current generator circuit by using a feedback arrangement to ensure a high PSRR of -75dB for the reference voltage. Temperature compensation is achieved by using the complementary to absolute temperature (CTAT) nature of gatesource of a MOSFET operating in the subthreshold region and proportional to absolute temperature (PTAT) nature of conventional composite pair architecture. The proposed CVR is designed in TSMC 180nm technology. The circuit works desirably for a supply range of 0.85V to 2.3V while generating a reference voltage of around 0.68V. Maximum temperature coefficient (TC) of 184 ppm/˚C and minimum TC of 69 ppm/˚C are noted for mismatch and process variations in the Monte-Carlo simulation for 1000 samples. The circuit consumes only 46nW of power, which makes it suitable for ultra-low power applications.

Abstract

This paper presents an ultra-low power CMOS voltage reference (CVR) which is free of amplifier and resistor. A current generator circuit is used to generate a supply independent current to bias the active load in the temperature compensation circuit. Drain-source voltage of two critical MOSFETs is made equal in the current generator circuit by using a feedback arrangement to ensure a high PSRR of -75dB for the reference voltage. Temperature compensation is achieved by using the complementary to absolute temperature (CTAT) nature of gatesource of a MOSFET operating in the subthreshold region and proportional to absolute temperature (PTAT) nature of conventional composite pair architecture. The proposed CVR is designed in TSMC 180nm technology. The circuit works desirably for a supply range of 0.85V to 2.3V while generating a reference voltage of around 0.68V. Maximum temperature coefficient (TC) of 184 ppm/˚C and minimum TC of 69 ppm/˚C are noted for mismatch and process variations in the Monte-Carlo simulation for 1000 samples. The circuit consumes only 46nW of power, which makes it suitable for ultra-low power applications. Keywords— CMOS voltage reference, Line sensitivity, Subthreshold region, Temperature compensation.

Abstract

The paper presents a sub-nW bandgap reference (BGR) that exploits the temperature variation of gate-leakage current in thin oxide devices operating in the accumulation region to generate the reference voltage. The incorporation of gateleakage transistors scales down the power consumption of the BGR to pico-watt level without using any large physical resistors or sophisticated techniques, thereby making it suitable for IoT applications. The BGR is designed in TSMC 65nm technology and occupies an area of 0.009mm 2 . Post layout simulation results show nominal and worst-case accuracies of 23ppm/°C and 44ppm/°C respectively in the temperature range of -40°C to 100°C. Without any trimming, an inaccuracy (±3σ) of 3% is observed for the reference voltage, showing its resilience to process variations. It also exhibits a typical line sensitivity of 0.063%/V in a supply range of 1.5V-3.8V and a PSRR of -65dB at DC and 1.8V supply. The power consumption is observed to be 443pW at 1.5V supply and nominal temperature

Abstract

The paper presents a sub-nW BJT based temperature sensor for ultra-low power microsystems. The sensor is based on amplifying the difference between base-emitter voltages of BJTs using gate-leakage transistors. Implemented in UMC 65nm technology, the sensor occupies an area of 0.005mm 2 . It achieves a maximum non-linearity error of 0.12 o C(3σ) over the temperature range of - 55 o C to 80 o C. Without any trimming, a worst case inaccuracy of +0.36 o C/ - 1.61 o C is observed w.r.t process variations, depicting the process-invariant nature of the temperature sensor. It also achieves a low supply sensitivity of 0.56 o C/V over a wide supply range of 0.7V-3V. The power consumption of the sensor is 419pW at 27 o C and 0.7V supply.

Abstract

This work presents a highly accurate current reference of 66nA for ultra-low power applications. A very low figure-of-merit (FOM) of 1.3501ppm/°C 2 is achieved on consuming a minimal quiescent current of 199.37nA. To cancel out process variations, the current subtraction technique is employed and a β-multiplier is used to compensate for mobility (μ) and threshold voltage (V th ). In addition, curvature compensation technique backed by PTAT and CTAT current cancellation is adopted to attain a lower temperature coefficient (TC). Hence, an imperceptible variation of accuracy with temperature and supply variations across all process corners is attained. An adopted trimming scheme further minimizes the overall process spread to ±1.515% without compromising on accuracy. Accordingly, a TC of 67.04ppm/°C over a wide temperature range of −50° C to 100° C is obtained. Furthermore, 1.413%/V line sensitivity (LS) in the supply range of 1.38V to 3V is observed. Low power consumption of 275.13nW@1.38V facilitates its use in high-performance low power applications.

Abstract

This brief presents a novel low-power and area-efficient LDO that satisfies all primary requirements of power mapping for a Power Management IC (PMIC). The design introduces a dynamically biased feedback resistor which responds instantly to the output voltage variations, thereby achieving better load transient behavior. Besides, the employed adaptive-biasing technique contributes in architectural transformation to attain stability over a wider range of load currents (0–100mA). It provides a regulated voltage of 1.87V from a supply ranging from 1.92V to 3.6V with a reported load and line regulation of 0.00136mV/mA and 0.078mV/V respectively. Moreover, the circuit potentially supports the load transients either from 0A to 100mA or 100mA to 0A with a rise and fall times of 10 μs. The achieved overshoot and undershoot values are 160mV and 154mV respectively. Hence, it demonstrates a substantial steady-state and transient performance with low-power thus making it suitable for battery-operated portable devices.

Abstract

Approximate Computing has paved way for elaborate savings in design area and latency of modern system architectures processing images or signals, by a deliberate yet tolerable loss of functional accuracy. This paper thus proposes a design of an approximate multiplier based on the efficient Toom-Cook algorithm, that has a lower complexity of O(N logd(zd−1) ) than O(N 2 ), for order d. Inherent integer divisions in the algorithm has restricted its feasibility in hardware, unless without suitable approximation. On an average, the proposed multiplier achieves 53%, 18% and 57% improvements in area, delay and power only with less than 1% mean error. Owing to these benefits due to lower computational complexity, the multiplier can be configured to achieve significant savings with a high quality output and that suits well to the nature of the speech processing systems, hence the design works well for the epoch extraction system in speech.

Abstract

In this paper, we propose an accurate and computationally efficient Gradient Boosting approach for the estimation of statistical variations aware leakage power and propagation delay in the CMOS/FinFET standard digital cells. The proposed model estimates the leakage power and propagation delay w.r.t variations in process, temperature (−55°C to 125°C) and supply voltage(±10% variations). The distinguishing feature of the proposed approach is its compatibility with both CMOS and FinFET technologies. Moreover, the performance of the proposed model is consistent with various technology nodes. Exhaustive tests report an average error of <1% in 16nm CMOS and FinFET standard digital cells w.r.t analog HSPICE simulations with several orders increase in computational speed. Further, the complex cell estimation can be carried out through precharacterized standard cells abstaining longer simulations.

Abstract

he paper presents an eight transistor (8T) pico-watt current reference with a novel method of rectifying the prob-lem of exponential power increase w.r.t temperature in traditionalsub-nW references. The proposed current reference is obtainedby modifying the traditional beta-multiplier architecture to scale-down the power consumption without sacrificing area. Theconstancy of power consumption w.r.t temperature is achievedby exploiting the voltage-current characteristics of a leakagetransistor in the modified architecture. The proposed currentreference, implemented in UMC 55nm technology, occupies anarea of0.00035mm2. It is designed for a current of 60pA andachieves an accuracy of19ppm/0Cover a wide temperaturerange of−550Cto1250C. The reported line sensitivity for thecurrent reference is 0.07%/V in the supply range of 1.2V - 4V.Post-trim results show a constant power consumption of 144pWw.r.t temperature and process variations @1.2V supply.

Abstract

This brief presents a novel PVT-invariant CMOS relaxation oscillator for Real-Time Clock (RTC) applications. The proposed design is compatible to work in a low supply voltage domain of SoC. The PVT invariance is achieved by a unique circuit implementation of introducing a self-adaptive mechanism that dynamically modifies the time constant of the oscillator core. Moreover, the design is accompanied by a digital calibration unit for further process compensation. Besides, the introduced supply independent bias circuit has greatly improved the supply regulation of the oscillator frequency. In addition, the design utilizes a complementary to absolute temperature (CTAT) current for temperature compensation. Area efficiency is enhanced by replacing bigger passive device i.e, resistor with an adaptive MOS resistor. The obtained results show that the minimum temperature coefficient (TC) of 31.236ppm/°C is achieved over a range of -40°C to 100°C. The resultant phase noise of -140dBc/Hz@1MHz is observed. The design has achieved a good power efficiency of 1.65nW/KHz at room temperature without a calibration unit. The line sensitivity (LS) of 0.1159%/V is noted in the range of 0.7V to 1.2V. Nevertheless, the entire system occupies an active area of 0.0509mm^2 with a power consumption of 90nW@0.7V. Also, the leakage current of the complete system is <; 54pA. Therefore, the proposed design aims at providing a production-friendly, ease of integration and low-cost solution.