Abstract

Random Number Generators (RNGs) are the solution for cryptographic applications to enhance hardware security. These RNGs ought to have three specific properties unpredictability, aperiodic, and good statistical criteria. This brief presents a True Random Number Generator (TRNG) based on Ring oscillators’ jitter with MLFSR. The MLFSR is augmented with a set of prime primitive polynomials, Boolean, and non-linear functions to attain a non-linear, unpredictable, and extended sequence period. Paper mainly focused on achieving high randomness by integrated the TRNG with a new promising crypto engine Keccak as a post-processing block; leads to extensively more security in data transfer, encryption keys, data authenticity of ICs, and IoT based applications. The RNG design is coded in Verilog HDL and implemented on the FPGA Zed board. Hashing is performed with a throughput of 2.4Gbps at 100 MHz either with RNG data or SHA data. Evaluated the randomness of the generated non-deterministic bitstreams (10 Mb) using the NIST 800–22 & Diehard test suite and successfully passed.

Abstract

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and dataintensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations.

Abstract

A Novel Smart Belt for Anxiety Detection, Classification, and Reduction Using IIoMT on Students’ Cardiac Signal and MSY

Abstract

This index covers all technical items—papers, correspondence, reviews, etc.—that appeared in this periodical during 2022, and items from previous years that were commented upon or corrected in 2022. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author’s name. The primary entry includes the coauthors’ names, the title of the paper or other item, and its location, specified by the publication abbrevia- tion, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author’s name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index.

Abstract

This paper presents the design, fabrication, and characterization of a thin-film Cr-Al-Cr (300 A°-1500 A°-300 A°) metal stack heater specially designed for chemical reactions which occur at a uniform temperature in the lab on a chip platform such as polymerase chain reaction (PCR) applications. The heater has been designed using COMSOL Multiphysics. The simulated design has been fabricated using lithography and patterning on a 5 × 5 cm2 glass substrate. For the validation of the proposed design thermal study of the fabricated heater has also been done using a FLIR IR camera. A very good agreement between the thermal image of modeled and fabricated heater has been achieved. This demonstrates the suitability of the proposed heater for PCR reaction applications.

Abstract

Electrocardiography (ECG) is a well-known noninvasive technique in medical science that provides information about the heart’s rhythm and current conditions. Automatic ECG arrhythmia diagnosis relieves doctors’ workload and improves diagnosis effectiveness and efficiency. This study proposes an automatic end-to-end 2D CNN (two-dimensional convolution neural networks) deep learning method with an effective DenseNet model for addressing arrhythmias recognition. To begin, the proposed model is trained and evaluated on the 97720 and 141404 beat images extracted from the Massachusetts Institute of Technology-Beth Israel Hospital (MIT-BIH) arrhythmia and St. Petersburg Institute of Cardiological Technics (INCART) datasets (both are imbalanced class datasets) using a stratified 5-fold evaluation strategy. The data is classified into four groups: N (normal), V (ventricular ectopic), S (supraventricular ectopic), and F (fusion), based on the Association for the Advancement of Medical Instrumentation® (AAMI). The experimental results show that the proposed model outperforms state-of-the-art models for recognizing arrhythmias, with the accuracy of 99.80% and 99.63%, precision of 98.34% and 98.94%, and F1-score of 98.91% and 98.91% on the MIT-BIH arrhythmia and INCART datasets, respectively. Using a transfer learning mechanism, the proposed model is also evaluated with only five individuals of supraventricular MIT-BIH arrhythmia and five individuals of European ST-T datasets (both of which are also class imbalanced) and achieved satisfactory results. So, the proposed model is more generalized and could be a prosperous …

Abstract

The present description relates to a method based on artifi cial intelligence to implement a wide range of microelec tronic circuits that can adapt by themselves to the usage conditions ( e.g. loading changes ) , manufacturing variances or defects ( e.g. process variations , device parameter mis matches , device model inaccuracies or changes , etc. ) , as well as environmental conditions ( e.g. voltage , temperature , interference ) in order to negate all or part of their effects on the circuit performance characteristics and achieve a very tight set of specifications over the wide range of conditions . Each microelectronic circuit is represented by a neural network model whose behavior is a function of the actual input signals , the usage and environmental conditions . An attached AI engine will infer from the model , the input signals , the usage conditions and the environmental condi tions and create the adaptive changes required to modify the microelectronic circuit's behavior to negate all or part of their effects on the circuit performance characteristics and to achieve a very tight set of specifications .

Abstract

This brief proposes an ultra-low-power current ref- erence in TSMC 180nm technology. Temperature compensation is achieved by taking the ratio of compensated voltage and an on-chip resistance. This design uses the concept of the back- gate effect of critical MOSFET to generate complementary to absolute temperature (CTAT) voltage. The circuit works from a supply voltage of 0.55V and is designed for a reference current of 5.6nA. Furthermore, a pseudo-differential amplifier (PD-AMP) helps realize low line regulation of 0.022%/V in the supply range of 0.55 to 1.9V. An average temperature coefficient (TC) of 256.07ppm/◦C is achieved for mismatch and process variations in Monte-Carlo simulations for 1000 samples over a tempera- ture range of −30◦C to 70◦C. The circuit consumes only 9.5nW of power (at room temperature and minimum supply voltage), making it suitable for ultra-low-power biomedical applications. Index Terms—Peaking current reference, biomedical, sub- threshold region, DIBL, PD-AMP.

Abstract

The paper presents a sub-nW gate-leakage based voltage and current reference in a single circuit whose reference values are scalable and doesn’t incorporate start-up circuits or resistors in the architecture. The power consumption of the proposed circuit increases by only 2.1x in the temperature range of -55°C to 100°C, unlike conventional voltage/current references where the power consumption increases exponentially w.r.t temperature. Implemented in 90nm technology, the proposed voltage reference (current reference) achieves post-trim typical accuracy of 22ppm/°C(58ppm/°C) and worst-case accuracy of 71ppm/°C(78ppm/°C). Excellent line sensitivities of 0.029%/V and 0.059%/V are observed for voltage and current reference respectively, in a supply range of 1V - 3V. Without any start-up circuit, the observed 99% settling times for voltage and current reference are 1.92ms and 2.526ms respectively. The area occupied by the total circuit is 0.0015mm 2 , while the power consumption is 156pW at typical corner, 27°C and 1V supply.

Abstract

The paper presents a low-cost method (no extra LDO, Op-amp) to increase the PSRR of composite pair based temperature sensor. Composite pair is a commonly used circuit to generate a linear PTAT voltage for a wide temperature range. A 180° phase shift, voltage biasing technique is introduced at the gate of the NMOS transistor to obtain a supply independent bias current in composite pair. The proposed technique thus achieves a high supply noise rejection. The circuit as a whole does not require additional circuitry, therefore it saves power and area. A 6μW Temperature sensor with 1mV/°c slope is designed in TSMC 180nm technology and achieves PSRR of -80dB. Post-layout simulation results show that the temperature sensor achieves inaccuracy of ±0.1°C from −55°C to 125°C, PSRR of −80dB at 105Hz and -70dB at 200kHz at 1V power supply, and the line regulation of 0.016%/V in a supply voltage range of 1V to 2.5V. Monte-Carlo simulation result for the output PSRR shows −80.56dB as the mean-value with a maximum deviation of ±1.5dB.