Abstract

This paper proposes a 162nW resistance-to-digital converter (RDC) for miniature battery-powered sensing systems. The RDC first converts input resistance to a pulse by charging a capacitor to a threshold voltage with a current proportional to the resistance. It compensates temperature sensitivity of the charging current by generating the threshold voltage with the same temperature dependency. Then, the circuit digitizes the pulse using an up-down counter that cancels temperature-dependent delay and offset of the low-power comparator in a digital Correlated Double Sampling (CDS) style. Designed in a 180 nm CMOS process, the proposed circuit achieves a figure-of-merit (FoM) of 0.845pJ/c.s. in simulation, with a conversion time of 50 ms for input resistance from to , while consuming 162nW at a supply voltage of 900 mV. Also, it obtains a temperature sensitivity of 26.9ppm/°C from −40 to 100°C

Abstract

Generative AI has seen remarkable growth over the past few years, with diffusion models being state-of-the-art for image generation. This study investigates the use of diffusion models in generating artificial data generation for electronic circuits for enhancing the accuracy of subsequent machine learning models in tasks such as performance assessment, design, and testing when training data is usually known to be very limited. We utilize simulations in the HSPICE design environment with 22nm CMOS technology nodes to obtain representative real training data for our proposed diffusion model. Our results demonstrate the close resemblance of synthetic data using diffusion model to real data. We validate the quality of generated data, and demonstrate that data augmentation certainly effective in predictive analysis of VLSI design for digital circuits.

Abstract

This paper presents a trim-free, low-power, and high-precision voltage/current reference for IoT and biomedical applications. The voltage reference is generated by the proper addition of CTAT and PTAT voltages, whereas, the current reference is generated using a MOSFET in the active region, which acts like a resistor and helps in lowering power consumption without increasing the form factor. Implemented in the 90nm CMOS process, the proposed voltage/current reference outputs a voltage and current of 820mV and 3.23nA, respectively. Without trimming, the process variation of the proposed voltage/current reference is 1.34%(σ/μ) / 1.75%(σ/μ) and the temperature coefficient of the voltage/current reference is 62ppm/oC / 332ppm/oC over the temperature range of -40oC to 100oC. The line sensitivity of the voltage/current reference is 0.296%/V / 0.414%/V for a wide supply range of 1V - 3.5V. The area occupied by the total circuit is 0.0112mm2, while the total power consumption of the design is 37nW at the typical corner of 27oC and 1V supply.

Abstract

—This paper presents a sub-1V, 593 pA current reference without using resistors and amplifiers. Temperature compensation is achieved by incorporating a CTAT gate to source voltage and a PTAT drain to source voltage in an NMOSbased sub-threshold biased circuit. The proposed architecture achieves ± 3σ/µ process variation of ± 0.75%, which enables seamless trim-free operation. Implemented in the 90nm CMOS process, the temperature-compensated current reference achieves a temperature coefficient of 378 ppm/oC over a high-temperature range of -40 to 100 oC and a line sensitivity of 0.198%/V in a supply voltage range from 0.8 to 2.5 V. Duty cycling technique is adopted in the CTAT generator to reduce the total average power consumption. The proposed circuit occupies an area of 0.074 mm2 while consuming only 3.3 nW at a typical corner of 27 oC and 0.8 V supply.

Abstract

This paper presents a low power voltage reference and current reference in one circuit. The reference voltage is the sum of the complementary to absolute temperature (CTAT) gatesource voltage of a MOSFET operating in the subthreshold region and a scaled version of the proportional to absolute temperature (PTAT) ΔVGS of two MOSFETs operating in subthreshold region. The generated temperature independent reference current is the ratio of the reference voltage and a resistance. The proposed circuit does not use an operational transconductance amplifier (OTA) to generate the reference current, thereby eliminates the variation in current due to any offset of the OTA. Furthermore, the circuit uses a native MOSFET for ameliorating the DC PSRR. The proposed circuit is designed in a 130nm CMOS process. The circuit works with a minimum supply voltage of 1.2V while generating a reference voltage of around 0.7V and a reference current of around 100nA. A TC of 100 ppm/˚C for the reference voltage and a TC of 108 ppm/˚C for the reference current are noted for mismatch and process variations from Monte-Carlo simulations for 300 samples. The circuit consumes only 240nW of power, which makes it suitable for ultra-low power applications.

Abstract

This paper proposes a low-power relaxation oscillator for low-power high-temperature IoT systems. It generates a 959 Hz clock signal from −40 to 170°C, consuming 6.75 nW at 0.65 V. A proposed switch-leakage compensation scheme nullifies the effects of body diode and subthreshold leakages on oscillator output frequency at high temperatures, thereby obtaining a wide operating temperature range. The oscillator implemented in a 180 nm CMOS process achieves a temperature coefficient of 40 ppm/°C from −40 to 170 °C at 0.65 V and a line sensitivity of 0.5 %/V from 0.65 to 2.4 V at room temperature, in simulation. Compared with state-of-the-art sub- μW oscillators, this circuit obtains the highest operating temperature and the maximum temperature range.

Abstract

Generative AI has seen remarkable growth over the past few years, with diffusion models being state-of-the-art for image generation. This study investigates the use of diffusion models in artificial data generation for electronic circuits to enhance the accuracy of subsequent machine learning models in tasks such as performance assessment, design, and testing when training data is usually known to be very limited. We utilize simulations in the HSPICE design environment with 22nm CMOS technology nodes to obtain representative real training data for our proposed diffusion model. Our results demonstrate the close resemblance of synthetic data using diffusion models to real data. We validate the quality of generated data and demonstrate that data augmentation is certainly effective in the predictive analysis of VLSI design for digital circuits.

Abstract

This paper presents a fast and efficient optimization engine with multi-directional, multi-objective algorithms based on a robust transistor sizing approach to improve digital circuit performance. However, such optimization processes are highly simulator-dependent and computationally expensive tasks. Therefore, we propose developing machine learning-based reliable models considering process and operating variations to speed up the optimization procedure by running them on developed Residual Neural Network (ResNN) models instead of running expensive circuit simulations. Results on 22nm Metal Gate HighK digital cells show a reduction in delay and leakage up to 36.7% and 18.8%, respectively improving computational efficiency by several orders.

Abstract

A system and method for synthesizing analog design in real - time using an artificial intelligence and machine learn ing ( AI / ML ) model are provided . The method includes ( i ) generating a behavioral model of an analog macro using the AI / ML model ; ( ii ) determining one or more operations that is required to implement the behavioral model by scanning the behavioral model ; ( iii ) selecting , using the AI / ML model , the analog macro based on at least one specification that corresponds to the analog macro ; ( iv ) synthesizing , the analog macro that is selected by the AI / ML model 214 and one or more leaf cells for each selected analog macro of the behavioral architectural implementation to obtain a gate level circuit design based on a figure of merit ( FoM ) of the analog macro and ( v ) determining , using the AI / ML model , the analog circuit design for the integrated circuit system based on the gate level circuit design that is synthesized .

Abstract

This paper presents a fast and efficient optimization engine with multi-directional, multi-objective algorithms based on a robust transistor sizing approach to improve digital circuit performance. However, such optimization processes are highly simulator-dependent and computationally expensive tasks. There-fore, we propose developing machine learning-based reliable models considering process and operating variations to speed up the optimization procedure by running them on developed Residual Neural Network (ResNN) models instead of running expensive circuit simulations. Results on 22nm Metal Gate High-K digital cells show a reduction in delay and leakage up to 36.7% and 18.8 %, respectively improving computational efficiency by several orders.