Abstract

Various studies have shown the advantages of using Machine Learning (ML) techniques for analog and digital IC design automation and optimization. Data scarcity is still an issue for electronic designs, while training highly accurate ML models. This work proposes generating and evaluating artificial data using generative adversarial networks (GANs) for circuit data to aid and improve the accuracy of ML models trained with a small training data set. The training data is obtained by various simulations in the Cadence Virtuoso, HSPICE, and Microcap design environment with TSMC 180nm and 22nm CMOS technology nodes. The artificial data is generated and tested for an appropriate set of analog and digital circuits. The experimental results show that the proposed artificial data generation significantly improves ML models and reduces the percentage error by more than 50% of the original percentage error, which were previously trained with insufficient data. Furthermore, this research aims to contribute to the extensive application of AI/ML in the field of VLSI design and technology by relieving the training data availability-related challenges.

Abstract

Approximate Computing techniques are finding a central role in modern applications, by optimizing architectures to relax some computation but with a constrained inaccuracy. In many applications, the FFT algorithm is invariably applied and there is a need for approximate low energy hardware solutions to the FFT. The paper thus proposes an approximate, fixed-point, in-place, shared memory architecture for FFT. It is well observed that the energy at FFT I/Os is not strictly contiguous, hence the proposed FFT exploits this window to tune the error. The proposed FFT and its associated butterfly unit is constructed to efficiently incorporate approximate Toom–Cook multiplication. As said, a supporting function in error correction based on the sparsity patterns, is a feature of this design. The design synthesized at 32 n m shows on average, a 48.6% and 52.8% improvement in consumption of area and energy, respectively …

Abstract

An evident challenge ahead for the integrated circuit (IC) industry is the investigation and development of methods to reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual, timeconsuming, and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-largescale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past toward VLSI design and manufacturing. Moreover, we discuss the future scope of AI/ML applications to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations.

Abstract

An Integrated Circuit with an automatically re-tuning analog circuit is provided. The Integrated Circuit comprises (a) an analog circuit comprising a plurality of tunable components each configured to respond to a plurality of change control bits, (b) a Process, Voltage Temperature (PVT) characteristics monitor comprising a plurality of PVT sensors, (c) a tuning memory embedded with a machine learning (ML) model of the analog circuit and (d) an artificial intelligence (AI) engine configured to receive a PVT signal input from the plurality of PVT sensors and the machine learning model embedded in the tuning memory. Each tunable component is configured to change its electrical characteristics such that together each of the tunable components is enabled to retune the analog circuit to attain a predefined set of electrical characteristics.

Abstract

A proportional to-absolute-temperature (PTAT) voltage generating circuit connected between a power supply voltage source and a ground for providing a PTAT voltage at an output terminal of the PTAT voltage generating circuit to act as a temperature sensor is provided. The PTAT voltage generating circuit includes a plurality of PMOS transistors. The plurality of PMOS transistors generates a second PTAT voltage by multiplying a first PTAT voltage by a factor equal to a ratio of a first equivalent resistance (R2) and a second resistance (R1) of a first PMOS transistor (M4). The first equivalent resistance (R2) is obtained from a series combination of the plurality of PMOS transistors. The first PTAT voltage is generated by determining a difference between a base-emitter voltage of a first PNP transistor (T1) and the second PNP transistor

Abstract

The paper presents a novel nW range gate-leakage-based Sub-Bandgap Voltage Reference (sub-BGR) for low-power and high-temperature range IoT applications. It generates a reference voltage of 336mV without incorporating any resistors and operating for a high-temperature range of −40°C to 150°C and a supply range of 0.7V-4V. In the above temperature and supply ranges, the proposed circuit's power consumption only goes up by 30x and 1.025x times, respectively. Designed in a 65nm CMOS process, the proposed architecture achieves an accuracy of 94ppm/°C. It achieves a line sensitivity of 0.0066%/V for a supply range of 0.7V to 4V and a PSRR of 89dB at DC and 1V supply. The proposed circuit shows a±3σ -inaccuracy of 4.295% without additional trimming circuits. It occupies only 0.0851mm2 area while consuming only 2.3nW at 27°C and 21.74nW at 150°C for a 0.7V supply.

Abstract

This paper presents a fully integrated ultra- low power trim-free current reference for wide-temperature applications. The proposed circuit doesn’t incorporate resistors, amplifiers, and start-up circuitry. A sub-threshold current-based curvature compensation is utilized to extend the temperature range. A process calibration technique is included to calibrate against process variations. Designed in a 55nm CMOS process for a temperature range of -55◦C to 150◦C, the current reference occupies an active area of 0.00458mm2. It achieves a line sensitivity of 0.06%/V for a supply range of 1.2-3.6V. The current produced is 250pA, with a temperature coefficient of 70ppm/oC at the typical corner.

Abstract

The paper presents a 0.5V supply, gate leakage-based current/voltage reference for ultra-low power IoT and biomedical applications. The references are generated by the proper addition of PTAT and CTAT curves, which are obtained by exploiting the traditional architecture of the beta multiplier and using the body biasing effect. Gate leakage transistors replace the resistors to ensure low power and low area. The circuit doesn't involve any Op-Amps avoiding the issues of offset that are prominent in these circuits. Implemented in CMOS 90nm technology, the proposed current (voltage) reference achieves a typical accuracy of 34.6ppm/∘C(29.68ppm/∘C) over a wide temperature range of −55∘C to 75∘C with typical value 63.32pA(0.35V). Excellent line sensitivity of 0.0318%N and 0.0576%N are observed for voltage and current reference, respectively, in a supply range of 0.5V - 2.3V. The area occupied by the total circuit is 0.0096mm2, while the power consumption is 415pW at the typical corner of 27∘C and 0.5V supply.

Abstract

This work introduces an ultra low power gm-boosted Colpitts voltage controlled oscillator (VCO) with a transformer based tank operating near 20 GHz. The proposed VCO is implemented in TSMC 65 nm CMOS technology. Through postlayout simulations, it is demonstrated that the proposed VCO exhibits a remarkable figure-of-merit of 196.26 dBc/Hz and achieves a phase noise of -111.21 dBc/Hz at a 1 MHz offset while operating at 19.6 GHz. Additionally, the VCO provides a tuning range of 1.7 GHz (18 - 19.7 GHz) and consumes only 1.2 mW of power from a 1 V supply.

Abstract

This paper proposes a switched-capacitor network (SCN) based fractional bandgap voltage reference (BGR) circuit designed in 180nm CMOS process to achieve high accuracy and low power consumption for implantable biomedical applications. The design proposes a VEB generator that employs a 2x charge pump and an improved SCN to generate a temperature inde-pendent reference voltage (VREF) ’. A low-power clock generator circuit is proposed, which reduces the leakage current by 37 % compared to previous works, thereby reducing the circuit's power consumption to 18.5nW at typical conditions. The design works from a supply voltage of 0.5V and has a TC of 74. Sppm/ ∘C over a temperature range of 0−80∘C . The PSRR of the circuit is -62.9dB at 100Hz. Based on the Monte Carlo simulations of 500 samples, we obtain an untrimmed 3σ/μ of 2.6%. The design occupies an active area of 0.027mm