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@inproceedings{bib_Leak_2025, AUTHOR = {Atmaram, Kudtarkar Sarang and Le, Khanh Minh and Abbas, Zia }, TITLE = {Leakestimator: a Unified Framework for PVT Aware Leakage Power Estimation in Digital Circuits}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2025}}

In this paper, we propose an efficient and robust framework for estimating leakage power while considering statistical variations in process parameters, supply voltage, and temperature (PVT) in FinFET-based digital circuits. Extensive testing reports an average error of less than 1 % in the ML models for standard digital cells, with an average MAPE (Mean Absolute Percentage Error) of 0.764%,0.770%, and 0.814% in the 7 nm,10 nm, and 16 nm FinFET technology nodes, respectively, which ensures a highly accurate leakage estimate for larger circuits. Additionally, we investigated the transistor-level approach, which distinctively estimates subthreshold, gate, and body leakage power using only transistor-level models and stacks, and investigated its trade-offs to gate-level models. Using ML techniques, we achieve a speedup of over 400 times compared to HSPICE for the characterization of digital blocks, using which complex cell designs can be analyzed across various input test combinations, significantly saving the time required for extensive simulations.

@inproceedings{bib_A_16_2025, AUTHOR = {Yerragudi, Shameer Basha and Pramod, Ashwin P and Yachareni, Santosh and Abbas, Zia }, TITLE = {A 16-Gb/s CTLE with Active Inductor Load and Feed-Forward Architecture in 28-nm CMOS for High-Speed Serial Links}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2025}}

A 16-Gb/s continuous-time linear equalizer (CTLE) is designed in 28-nm CMOS technology, featuring an active inductor load and feedforward compensation to enhance high-frequency performance. The proposed design features a power-efficient architecture, achieving a remarkable eye opening of 45.75 ps and a vertical differential eye opening of 781.19 mV. The design achieves reliable operation for channel losses of 9 dB, consuming a total power of 3.3 mW from a 0.9 V supply. This CTLE provides an energy-efficient solution for high-speed SerDes applications, with a calculated figure-of-merit of 0.022 pJ/hit/dB.

@inproceedings{bib_RelO_2025, AUTHOR = {Akhtar, Mohammad Rehan and Goswami, Ritwik Basyas and Abbas, Zia }, TITLE = {RelOps: Reliability Optimization in Standard Cells across PVT Variations in FinFET Digital Circuits}, BOOKTITLE = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}. YEAR = {2025}}

FinFET, now firmly established in leading VLSI industries for their superior performance, exhibit heightened aging susceptibility that poses significant reliability challenges. The aggressive scaling of technology nodes has further compromised circuit reliability in recent years, highlighting the need for effective aging mitigation techniques. Recent advancements in the miniaturization of nanoscale technology have demonstrated the potential of optimizing performance parameters in standard cells using machine learning models and optimization algorithms through device sizing modifications. Building on this progress, we propose a methodology for optimizing performance parameters in 16nm high-performance (HP) FinFET for the first time. The approach leverages a multi-objective optimization algorithm framework to mitigate aging impacts across PVT variations while addressing NBTI and HCI effects by optimally adjusting FinFET design parameters, including channel length (lg), width (tfin), and height (hfin). With SPICE simulations, time-series datasets were generated to train machine learning models that achieved an R² score exceeding 0.99 and a mean absolute percentage error below 1% across standard cells. Our approach yields a significant simulation speedup and a reduction in simulation workload compared to traditional SPICE simulations. Using the proposed optimization algorithm framework, we improved the power-delay product (PDP) by up to 36.97% under non-aging conditions and 34.94% with aging considered with respect to the nominal dimension at the fresh year, demonstrating significant performance gains for FinFET-based standard cells. The experimental results on 12 distinct complex cells validate the aging mitigation across years.

@inproceedings{bib_Arti_2025, AUTHOR = {Munir, Farwa and Chopra, Hitesh and Heyat, Md Belal Bin and Abbas, Zia }, TITLE = {Artificial intelligence in globesity research: diagnosis, treatment, and prevention solutions for a healthier world with future recommendations}, BOOKTITLE = {International Journal of Systems Assurance Engineering and Management}. YEAR = {2025}}

Globesity has widely affected the world population. It is a multifactorial health problem. Obesity can be caused by high-fat intake, high-calorie intake, physical inactivity, age, gender, or hormonal issues that can induce many health issues, such as cardiovascular disorders, diabetes, and metabolic disorders. Health facilities are insufficient to provide services to the whole population. In such a case, introducing Artificial Intelligence (AI) in the health sector is one of the most significant steps that can be taken. With the help of AI, the prognosis, diagnosis, and treatment can be provided to individuals within their homes and setups without any physical interactions. Assembling the data collected with AI can help to give more information on the type of obesity prevailing in a particular society so that it could be prevented in the population. Since AI learning is relatively novel within the existing system of medicine, enabling …

@inproceedings{bib_SYST_2025, AUTHOR = {Le, Khanh Minh and Abbas, Zia }, TITLE = {SYSTEM AND METHOD FOR ON DEMAND SPECIFICATION OF ANALOG ICs USING AI MODELS}, BOOKTITLE = {United States Patent}. YEAR = {2025}}

A method for describing, distributing and re-producing specifications of analog IC using AI models, is fulfilled in the ongoing description by (a) creating an AI model to represent the electrical specifications of the analog integrated circuit over a specified range of PVT, input and output loading, and aging conditions,(b) training the AI model with simulation data associated with the analog IC, wherein the simulation inputs include a plurality of instances of PVT (Process, Voltage, Temperature), input/output loading, and aging conditions,(c) electronically enabling peripheral functions with the AI model into an AI model pack, wherein the peripheral functions include a set of computer code modules to extract the AI model, perform user requested operations, calculate specifications of the analog IC on-the-fly and interact with the user, and (d) distributing the encrypted AI model pack to a plurality of users.

@inproceedings{bib_Low-_2025, AUTHOR = {Abhishek, P V and ALI, HULUVALLAY MOHAMMED ASHFAKH and Jain, Arpan and Le, Inhee and Abbas, Zia }, TITLE = {Low-Power Voltage Reference: Review & Progress}, BOOKTITLE = {IEEE VLSI Test Symposium}. YEAR = {2025}}

This paper explores advanced voltage reference designs with extremely low power consumption, specifically under one microwatt. These designs are crucial for portable electronic systems that rely on minimal power. The paper categorizes these voltage references based on the types of devices used to generate temperature-proportional or complementary signals. It also provides key design examples to illustrate these concepts. Additionally, the paper enhances understanding by conducting a comparative analysis of performance metrics, including power consumption, temperature coefficient, physical size, and resistance to variations in the manufacturing process.

@inproceedings{bib_A_bi_2025, AUTHOR = {Vajrala, Abhinav and M, RAJESH and Yachareni, Santosh and Abbas, Zia }, TITLE = {A bidirectional frequency detector independent of input transition density for a wide-tuning range applications}, BOOKTITLE = {International Symposium on Circuits and Systems}. YEAR = {2025}}

This paper presents a dual-loop reference-less Clock and Data Recovery (CDR) architecture implemented in TSMC 28nm CMOS process for PCIe Gen4 application. A novel frequency detector (FD) with a wide frequency acquisition range is presented, which avoids harmonic locking issues and is independent of input transition density. The FD demonstrates rapid locking capabilities, securing synchronization with Pseudo-Random Binary Sequences (PRBS7 and PRBS31) data patterns. The locking time from PCIe Gen1 (2.5Gbps) to PCIe Gen4 (16Gbps) is less than 5us. The CDR achieves a power consumption of less than 2mW with a supply voltage of 0.9V.

@inproceedings{bib_Zero_2025, AUTHOR = {AMURU, DEEPTHI and Abbas, Zia }, TITLE = {Zero-shot Learning in Performance Prediction of Digital VLSI Circuits}, BOOKTITLE = {International Symposium on Circuits and Systems}. YEAR = {2025}}

The heightened sensitivity of circuit behavior to manufacturing processes is surging in sub-nanometer nodes, presenting a formidable challenge for high-dimensional performance modeling. Estimating circuit performance variations resulting from process randomness in upcoming technology nodes aids in implementing appropriate countermeasures to handle them. Addressing this, we introduce a multi-node transfer learning method for predicting the performance of VLSI digital circuits. The proposed method facilitates Zero-shot Learning in future technology nodes based on insights gained from analyzing the circuit’s process-induced behavior in established nodes. The approach is fast, scalable, and robust, leveraging digital standard cell characterization that can be applied to estimate the performance of a wide array of intricate circuits. Experimental results affirm the approach’s exceptional data efficiency, achieving a speed increase of up to 104 times, all the while maintaining superior accuracy compared to traditional simulators.

@inproceedings{bib_Towa_2025, AUTHOR = {AMURU, DEEPTHI and Mittal, Chetan and Abbas, Zia }, TITLE = {Towards Designing a Unified DNN Architecture for Analog and Mixed-Signal Circuit Characterization}, BOOKTITLE = {International Symposium on Circuits and Systems}. YEAR = {2025}}

Analog circuit characterization is a pivotal phase in the design process, serving to validate their performance. It ensures that design choices lead to optimization, ultimately resulting in reliable and robust designs. The conventional, resource-intensive circuit characterization using traditional simulation tools is being supplanted by Machine Learning surrogate models, providing computational advantages. Nevertheless, these models tend to be specific to particular circuits, demanding significant design efforts and often lacking reusability for other designs and topologies. In this paper, we introduce a Unified Neural Network Architecture that is versatile and computationally efficient. It offers a streamlined and effective approach for modeling a diverse array of analog circuits prone to process, voltage, and temperature variations. Experimental trials conducted on various circuits in CMOS 180nm, 65nm and 28nm technologies demonstrate a mean average percentage error of less than 1%, affirming the effectiveness and reusability of the proposed architecture. This leads to substantial savings in design time, computational resources, and characterization costs.

@inproceedings{bib_C-Ar_2025, AUTHOR = {Goswami, Ritwik Basyas and Akhtar, Mohammad Rehan and Zahra, Andleeb and Abbas, Zia }, TITLE = {C-Arch: Chained Architecture towards Foundation Modeling of CMOS/FinFET Circuit Designs}, BOOKTITLE = {International Symposium on Circuits and Systems}. YEAR = {2025}}

Modeling process, operating condition, reliability, and technological variation in transistor level design introduce significant variance in device and performance parameters. This paper presents a machine-learning-based architectural approach that enhances model performance, as a step towards developing Foundation Models tailored for circuit data, accurately capturing technology and process-induced variations in leakage power, voltage, and current. The architecture incorporates the impact of varying operating conditions, including temperatures from -55°C to 125°C and supply voltage fluctuations of ±10% on 16nm HP FinFET, and 16nm, 22nm, 32nm, and 45nm HPMGK CMOS technology nodes. By enhancing the performance of baseline machine-learning models using a chained architecture to cater to the high variance in target, our C-Arch serves as a versatile framework for circuit modeling when the data spread is high. Experimental results on current, voltage, and leakage power estimation, demonstrate average improvements of up to 93.76%, 96.17%, and 88.82% in Mean Absolute Percentage Error compared to baseline models, underscoring the computational savings and viability of Foundation Models in circuit design.

@inproceedings{bib_Rand_2025, AUTHOR = {AMURU, DEEPTHI and Ahmad, Amir and Abbas, Zia }, TITLE = {Randomized processes to create diverse models for One-class classifier ensembles}, BOOKTITLE = {Applied Soft Computing}. YEAR = {2025}}

One-class classification (OCC) is a machine learning technique employed in scenarios involving imbalanced data, limited labeled data, or the need to detect anomalies or novel patterns. One-Class Classification by Ensembles of Regression (OCCER) models have shown excellent performance for OCC problems. In this paper, we study whether the combinations of ensemble methods such as random subspace and random projection with OCCER can be used to improve the performance of OCCER. Our main objective is to explore the impact of diversity creation methods, including bagging, random subspace, and random projections, on enhancing the performance of the OCC ensemble method. Additionally, we investigate the feasibility of applying the OCCER ensemble method to a novel low-dimensional space generated by autoencoders, all while maintaining high prediction accuracy. The experimental results over 37 datasets demonstrate that the creation of diverse OCCER models using random subspace and random projection substantially improves the performance of the OCCER. The diversity creation method, Random subspaces, outperforms other diversity creation methods.

@inproceedings{bib_"A_P_2024, AUTHOR = {Saraswat, Mehul Kumar and Mahadev, Rajesh and Yerragudi, Shameer Basha and Le, Khanh M and Abbas, Zia }, TITLE = {"A Process and Temperature Compensation Technique for Ring-VCO in Charge-Pump PLL" in MWSCAS-2024.}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2024}}

Voltage-Controlled Oscillator (VCO) is a crucial component of a Phase-Locked Loop (PLL) system. However, the frequency of a typical Ring-Oscillator-based VCO varies by about 2–3 times across its frequency tuning range and process, voltage and temperature (PVT) conditions. The gain of a Ring-VCO is another crucial parameter that is significantly affected by PVT variations, thereby impacting the stability and loop bandwidth of the PLL. This paper describes a compensation technique to minimize variations in Ring-VCO gain across PVT conditions. A Charge-Pump PLL operating at 4 GHz is implemented in a 28nm CMOS process. The gain of the Ring-VCO varies by ±27% across PVT at 4 GHz. This gain variation of Ring-VCO combined with other PVT-dependent blocks of PLL lead to a deviation of ±60% in Loop Bandwidth and ±21 % in Phase-Margin (PM). Process trimming reduces the VCO gain variation to ±25 %. Subsequently, the temperature compensation technique reduces the VCO gain variation by 3 times to ±8 %, over a temperature range −40∘C to 125∘C . The resulting variations in Loop Bandwidth and Phase-Margin are reduced to ±34%” and ±l5%” respectively.

@inproceedings{bib_SELF_2024, AUTHOR = {Abbas, Zia and Le, Khanh M and De, Koushik and AMURU, DEEPTHI }, TITLE = {SELF-ADAPTING ANALOG CIRCUIT DESIGN METHOD AND SYSTEM}, BOOKTITLE = {United States Patent}. YEAR = {2024}}

A method and system based on machine learning to create self-adapting analog circuits adapted to change their internal components on-the-fly in response to changes in process, voltage, and temperature to re-tune the electrical characteristics back to nominal specified values is disclose. The method and system herein comprise of designing the analog circuit, generating simulation data for machine learning, creating a full query database, creating and training, using simulation results, a machine learning (ML) model of the circuit and applying the ML model to infer the required changes to internal components of the analog circuit in response to changes in P, V, and T conditions. With this method and system, evaluation of the adverse effects of PVT changes, decision on internal circuit changes, and realization of requisite design changes are performed by the computer system solely within a ML data domain

@inproceedings{bib_Low__2024, AUTHOR = {Abbas, Zia and Yadav, Battu Balaji and Mounika, Kelam }, TITLE = {Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance}, BOOKTITLE = {INDIAN PATENT}. YEAR = {2024}}

Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance

@inproceedings{bib_A_0._2024, AUTHOR = {Mittal, Chetan and Dey, Arnab and Banerjee, Anubhab and Abbas, Zia }, TITLE = {A 0.8-V, 593-pA Trim-free Duty-cycled All CMOS Current Reference for Ultra-Low Power IoT Applications}, BOOKTITLE = {International Conference on VLSI Design}. YEAR = {2024}}

This paper presents a sub-1V, 593 pA current reference without using resistors and amplifiers. Temperature compensation is achieved by incorporating a CTAT gate to source voltage and a PTAT drain to source voltage in an NMOS-based sub-threshold biased circuit. The proposed architecture achieves process variation of ±0.75%, which enables seamless trim-free operation. Implemented in the 90nm CMOS process, the temperature-compensated current reference achieves a temperature coefficient of 378 ppm/°C over a high-temperature range of −40 to 100°C and a line sensitivity of 0.198%/V in a supply voltage range from 0.8 to 2.5 V. Duty cycling technique is adopted in the CTAT generator to reduce the total average power consumption. The proposed circuit occupies an area of 0.074 mm 2 while consuming only 3.3 nW at a typical corner of 27 °C and 0.8 V supply.

@inproceedings{bib_A_Tr_2024, AUTHOR = {Atmakuri, Aniketh and Vulichi, Soma Satya Pradhith and Gopal, Jalluri Ram and Vishnu, Kuncham and Mittal, Chetan and Abbas, Zia }, TITLE = {A Trim-Free PVT Invariant Current Reference with 0.48% Process Inaccuracy Using VTH Tracking Approach}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2024}}

The prevalence of MOSFETs in diverse electronic applications highlights their significance. However, the sensitivity of MOSFET threshold voltage to process variation poses a substantial challenge in achieving consistent device performance. This paper proposes a novel approach to overcome this challenge by employing a threshold voltage (VTH) tracking circuit that tracks the variation in VTH. Our primary objective is to develop a current reference that remains invariant across process, voltage, and temperature (PVT) variations, eliminating the need for an external trimming circuit. This is achieved by the meticulous integration of VTH tracking circuit, CTAT generator, PTAT generator, and a current adder. By employing this design,a process variation (σ/µ) of 0.48%, a temperature coefficient (TC) of 210ppm/ ◦C for a temperature range of −40◦C to 120◦C, and a line sensitivity of 1.6% is achieved over a voltage range of 1.6V − 3V. The proposed circuit occupies an area of 0.013mm2 while consuming power of 56µW at a typical corner of 27◦C and a supply of 1.8V. The given circuit is implemented in a 180nm CMOS process node with a generated reference current of 61nA.

@inproceedings{bib_Desi_2024, AUTHOR = {Sharma, Shiva and De, Koushik and Abbas, Zia }, TITLE = {Design and Optimization of Robust Process Monitors}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2024}}

This paper presents a new approach to efficient process monitor (PMON) design. It focuses on robust process tracking of PMOS and NMOS devices while minimizing the effects of external factors such as die temperature variations and local supply voltage changes. The proposed design method introduces a comprehensive set of PMON libraries tailored for the specific device types provided by a target technology node. Central to this method is a novel design automation routine based on Zero Temperature Coefficient (ZTC) biasing of a ring oscillator-based PMON. This work demonstrates the effectiveness and scalability of the proposed method across multiple process nodes. The generated PMON structures show a multi-fold improvement in sensitivity for process tracking compared to current state-of-the-art solutions.

@inproceedings{bib_A_0._2024, AUTHOR = {Mittal, Chetan and Gopal, Jalluri Ram and Abbas, Zia }, TITLE = {A 0.6 V, 13nW, 0.0012%/V Line Sensitivity PVT-Invariant Voltage Reference Without Using Resistors and Amplifiers}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2024}}

This paper presents a low-voltage, low-power PVT-invariant voltage reference with excellent line sensitivity for IoT and biomedical applications. By applying a bias current in an NMOS-based composite pair and bias voltage at the body of NMOS to get the temperature-compensated voltage reference over a wide temperature range. The proposed design implemented in a 180nm CMOS process gives an output of 141mV which is independent of process, voltage, and temperature. Without trimming, the process variation of the proposed design is 0.988% , and the temperature coefficient of the proposed voltage reference is over a wide temperature range of to . For a supply voltage ranging from 0.6V the line sensitivity of the reference is 0.0012%N.

@inproceedings{bib_Tran_2024, AUTHOR = {AMURU, DEEPTHI and Kumar, Vechalapu Raja Mavullu and Abbas, Zia }, TITLE = {Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation}, BOOKTITLE = {ACM Transactions on Design Automation of Electronic Systems}. YEAR = {2024}}

Designing robust performance models for modern complex digital circuits in the face of rapidly accelerating process variations is a critical yet demanding task. This paper introduces an efficient statistical performance modeling approach for VLSI digital circuits that incurs minimal computational expense. The fundamental concept involves capitalizing on knowledge gained from circuit modeling in one technology node to streamline the modeling process in another. This is achieved by merging previously established statistical models of process technology with a limited set of simulation data from a subsequent process technology through transfer learning. Comprehensive experiments conducted across diverse technology nodes demonstrate that the proposed framework is robust, precise, efficient in data usage, and computationally superior to other cutting-edge performance modeling techniques.

@inproceedings{bib_A_10_2024, AUTHOR = {Jain, Arpan and ALI, HULUVALLAY MOHAMMED ASHFAKH and Abhishek, P V and Lee, Inhee and Abbas, Zia }, TITLE = {A 100-Hz, 2nW RC Oscillator Using Resistance Amplifier}, BOOKTITLE = {European Conference on Solid-State Circuits}. YEAR = {2024}}

This paper introduces an ultra-low-power RC oscillator that utilizes a resistance amplification technique. The resistance amplifier achieves the effect of a large resistance by amplifying the I-V characteristics of a small resistance, resulting in significant area savings. To improve precision in oscillation frequency, a continuous time auto-zeroing technique is incorporated to dynamically calibrate the offset voltage of an integrated amplifier. Fabricated using a 180−nm CMOS process, the designed oscillator produces a 100−Hz clock signal while consuming only 2 nW power under compact silicon area (0.12mm2). Additionally, it achieves a competitive temperature coefficient (TC) of 280ppm/∘C and line sensitivity (LS) of 1.1 % / V without the need for any calibration.

@inproceedings{bib_A_la_2024, AUTHOR = {Zahra, Dr. Andleeb and Sinha, Swarnim and Modak, Alimpan and Siddiqui, Imran and Syed, Azeemuddin and Bhimalapuram, Prabhakar and Sau, Tapan Kumar and Kumar, Pawan and Abbas, Zia }, TITLE = {A label-free sensing of creatinine using radio frequency-driven lab-on-chip (loc) system}, BOOKTITLE = {Engineering Research Express}. YEAR = {2024}}

Skip to content IOP Science home Accessibility Help Search Journals Books Publishing Support Login Engineering Research Express Inclusive Publishing Trusted Science, find out more. Purpose-led Publishing, find out more. ACCEPTED MANUSCRIPT A label-free sensing of creatinine using radio frequency-driven lab-on-chip (loc) system Andleeb Zahra1, Swarnim Sinha2, Alimpan Modak3, Imran Siddiqui4, Azeemuddin Syed5, Prabhakar Bhimalapuram6, Tapan K. Sau7, Pawan Kumar8 and Zia Abbas9 Accepted Manuscript online 2 August 2024 • © 2024 IOP Publishing Ltd What is an Accepted Manuscript? DOI 10.1088/2631-8695/ad6ad5 DownloadAccepted Manuscript PDF Download PDF Article metrics 6 Total downloads Submit Submit to this Journal Permissions Get permission to re-use this article Share this article Article and author information Abstract This paper presents a promising avenue of Radio Frequency (RF) biosensors for sensitive and real-time monitoring of creatinine detection. Knowing creatinine levels in the human body is related to its possible association with renal, muscular, and thyroid dysfunction. The detection was performed using an Inter-Digitated Capacitor (IDC) made of copper (Cu) metal over an FR4 substrate. To demonstrate our methodology, we have chosen Phosphate Buffer (PB) as our solvent for making the creatinine solutions of different concentrations. Moreover, Assayed Chemistry Control (ACC), a reference control consisting of human serum-based solutions has been mixed with the different concentrations of creatinine in a ratio of 1:9 to spike the creatinine value in the ACC solution. The sensor has been designed using a High-Frequency Structure Simulator (HFSS) tool with an operating frequency of 2.53 GHz. Then the design is fabricated over the FR4 printed circuit board (PCB) and tested using a Vector Network Analyzer (VNA). However, the sensitive area of the IDC is introduced to grade 4 Whatman filter paper for the Sample Under Test (SUT) handling unit. The main advantage of using Whatman filter paper is that the uniform spreading of liquid reduces experimental error, and less volume is required for testing the sample. The principal idea implemented in the biosensor design is to track the shift in the operating frequency in the presence of different concentrations of creatinine mix in ACC solution with Phosphate Buffer (PB) solution as a reference.

@inproceedings{bib_A_Th_2024, AUTHOR = {Ahmad, Amir and Abbas, Zia }, TITLE = {A Theoretical Study of the Representational Power of Weighted Randomised Univariate Regression Tree Ensembles}, BOOKTITLE = {Journal of Information and Knowledge Management}. YEAR = {2024}}

Univariate regression trees have representation problems for non-orthogonal regression functions. Ensembles of univariate regression trees have better representational power. In some cases, weighted ensembles have shown better performance than unweighted ensembles. In this paper, we study the properties of ensembles of regression trees by using regression classification models. We propose a theoretical framework to study the representational power of infinite-sized weighted ensembles, consisting of randomised finite-sized regression trees. We show for some datasets that the weighted ensembles may have better representational power than unweighted ensembles, but the performance is highly dependent on the weighting scheme and the properties of datasets. Our model cannot be used for all the datasets. However, for some datasets, we can accurately predict the experimental results of ensembles of regression trees.

@inproceedings{bib_A_27_2024, AUTHOR = {Dey, Arnab and Sahishnavi, Bhartipudi and Banerjee, Anubhab and Abbas, Zia and Zahra, Andleeb }, TITLE = {A 275 pW, 0.5 V supply insensitive gate-leakage based current/voltage reference circuit for a wide temperature range of −55 to 100 °C without using amplifiers and resistors}, BOOKTITLE = {Microelectronic Journal}. YEAR = {2024}}

The paper presents a 0.5 V, ultra-low power current, and voltage reference circuit in a single block, giving reference values of 90.7 pA and 288 mV. The proposed block uses proper addition of CTAT and PTAT curves, resulting in an excellent temperature coefficient of 15.2 ppm/°C and 36.8 ppm/°C for compensated current and voltage values, respectively, at a nominal supply of 0.5 V for a wide temperature range of −55 °C to 100 °C. Usage of gate leakage transistors in place of resistors helps in reducing the power and area of the circuit to 0.087 mm2. The circuit is implemented in 90 nm technology and operates effectively across a wide voltage range of 0.5 V–2.6 V with a supply sensitivity of 0.028 %/V and 0.154 %/V for current and voltage reference, respectively. The entire circuit takes a power of 275.26 pW at nominal conditions.

@inproceedings{bib_Qual_2024, AUTHOR = {Srivastava, Prasha and Kumar, Pawan and Abbas, Zia }, TITLE = {Qualitative Data Augmentation for Performance Prediction in VLSI Circuits}, BOOKTITLE = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems}. YEAR = {2024}}

Various studies have shown the advantages of using Machine Learning (ML) techniques for analog and digital IC design automation and optimization. Data scarcity is still an issue for electronic designs, while training highly accurate ML models. This work proposes generating and evaluating artificial data using generative adversarial networks (GANs) for circuit data to aid and improve the accuracy of ML models trained with a small training data set. The training data is obtained by various simulations in the Cadence Virtuoso, HSPICE, and Microcap design environment with TSMC 180 nm and 22 nm CMOS technology nodes. The artificial data is generated and tested for an appropriate set of analog circuits and digital cells. The experimental results show that the proposed artificial data generation significantly improves ML models and reduces the percentage error by more than 50% of the original percentage error, which were previously trained with insufficient data. Furthermore, this research aims to contribute to the extensive application of AI/ML in the field of VLSI design and technology by relieving the training data availability-related challenges.

@inproceedings{bib_A_Si_2024, AUTHOR = {Jain, Arpan and ALI, HULUVALLAY MOHAMMED ASHFAKH and Akula, Dheekshith Kumar and Abhishek, P V and Abbas, Zia }, TITLE = {A Single-Point, Auto-Calibration Technique For PTAT/CTAT Resistance Based Current References}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2024}}

In this paper, a cost-effective and easy-to- implement auto-trim technique is introduced for PTAT or CTAT resistance based current references. The resistance with a process-insensitive temperature coefficient requires only a single point trim at room temperature, achieving process and temperature-insensitive current. The approach utilizes a data comparison method where on-chip current data is compared with off-chip reference data to trim the resistance of the current reference. The off-chip reference data is generated using a low-cost external resistor that is used only during the trimming operation. The proposed trimming sensor effectively calibrates the current, offering precision close to manual trimming, leading to cost, time, and resource savings. To validate the working of the proposed technique, the auto trim sensor with on-chip current reference is designed in TSMC 180nm technology. The auto trim sensor calibrates the on-chip current from ±25% (due to voltage and resistance process variation) to ±1.5% across the process and 3σ mismatch

@inproceedings{bib_Enha_2024, AUTHOR = {Srivastava, Prasha and Kumar, Pawan and Abbas, Zia }, TITLE = {Enhancing ML Model Accuracy for Digital VLSI Circuits Using Diffusion models: a Study on Synthetic Data Generation}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2024}}

@inproceedings{bib_Cons_2024, AUTHOR = {Abbas, Zia and Abhishek, P V and ALI, HULUVALLAY MOHAMMED ASHFAKH and Jain, Arpan }, TITLE = {Constant Reference Voltage/Current Generating Circuit}, BOOKTITLE = {INDIAN PATENT}. YEAR = {2024}}

A constant reference voltage/current generating circuit connected between a power supply voltage source and a ground that provides a constant reference voltage/current at an output terminal. The constant reference voltage/current generating circuit includes one or more transistors that generates the constant reference voltage by determining a difference between a gate-source voltage of a first transistor and a gate source voltage of a second transistor with respect to a temperature. The constant reference voltage is mirrored at the output terminal of the constant reference voltage/current generating circuit using a current mirror circuit. The current mirror circuit is connected to the constant reference voltage/current generating circuit.

@inproceedings{bib_On_C_2024, AUTHOR = {Jain, Arpan and ALI, HULUVALLAY MOHAMMED ASHFAKH and Abbas, Zia }, TITLE = {On Chip Complementary Metal Oxide Semiconductor (CMOS) Resistance Amplifier}, BOOKTITLE = {INDIAN PATENT}. YEAR = {2024}}

An on-chip resistance amplifier which amplifies the resistance of a small on-chip resistor in die size is provided. The amplifier is a two-terminal circuit of which a high voltage terminal ranging from 0.4 Volts to 3.6 Volts and a second low voltage terminal at the ground includes a small on-chip resistor, a Voltage divider, an operational amplifier op-amp, a NMOS transistor. The voltage divider works in ultra-low power. The voltage (V) at high voltage terminal is divided by some gain A which is V/A, a second voltage. The second voltage is given to the on-chip resistor R. The current generated by on-chip resistor is passed through the higher voltage terminal and the resistance seen at the higher terminal is the amplified resistance of A*R.

@inproceedings{bib_An_i_2024, AUTHOR = {Agarwal, Samriddhi and Yerragudi, Shameer Basha and D, Naveen and Zahra, Andleeb and Bhimalapuram, Prabhakar and Syed, Azeemuddin and Abbas, Zia }, TITLE = {An inductor-less, cost-effective On-chip CMOS VNA for bio-molecule detection}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2024}}

Biomolecules play indispensable roles in all life processes, including disease development, so their accurate detection is critical to cell investigation, medical diagnosis, and treatment. Radio Frequency (RF) sensing has become a popular testing technique compared to traditional methods for biomolecule analysis, providing results in less time using less volume of samples. It allows rapid, sensitive, real-time measurements and label-free techniques. However, for taking the signals from biomolecules over the RF-based sensors we need to connect them with the Vector Network Analyzer (VNA) which is a bulky and costly device. To develop an RF sensing based a true lab-on-chip (LoC) device, the paper presents a fully integrated low-power less-area on-chip single port CMOS VNA designed in 65nm CMOS technology to detect the bio-molecule The proposed design works in a tunable frequency range of 0.5 GHz to 2.5 GHz, ensuring much higher precision. Using an RLC equivalent of an Interdigitated capacitor (IDC) sensor, a fully integrated architecture for detecting $S_{11}$ of the biomolecules has been introduced. A resistive bridge coupler is used for wideband operation with a directivity of 14.89dB up to 2.5 GHz. Also, a high-linearity LNA (low noise amplifier) is designed with a linearity of -13dB and a gain of 14dB. The LNA has a low NF of 3.21dB. The design occupies an active area of 0.01767mm^2 and consumes power of 41mW from a 1 V supply.

@inproceedings{bib_Meta_2024, AUTHOR = {Raghavendra, N V and AMURU, DEEPTHI and Abbas, Zia }, TITLE = {MetaCirc: a Meta-Learning Approach for Statistical Leakage Estimation Improvement in Digital Circuits}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2024}}

Aggressive scaling down of transistor dimensions has made process-aware circuit modeling a crucial task. Achieving accurate circuit modeling requires lengthy and resource intensive simulations. Machine Learning-based surrogate models, offering computational efficiency and speed, are viable alternatives to traditional simulators. This paper introduces a meta-learning approach designed to accurately capture process induced variations in the leakage power of VLSI circuits. The impact of a wide range of fluctuations in operating conditions, including temperature (-55°C to 125°C) and supply voltage (±10%) has also been incorporated for leakage modeling. The proposed meta-learning model is versatile, enhancing the performance of underlying baseline machine learning models while eliminating the need for time-consuming hyperparameter optimization. Our experiments on leakage estimation using 16 and 7 nanometer FinFET technology nodes demonstrate an average improvement of up to 50% and 48% in Mean Absolute Percentage Error compared to stand-alone baseline models.

@inproceedings{bib_Enha_2023, AUTHOR = {Srivastava, Prasha and Kumar, Pawan and Abbas, Zia }, TITLE = {Enhancing ML model accuracy for Digital VLSI circuits using diffusion models: A study on synthetic data generation}, BOOKTITLE = {Neural Information Processing Systems Workshops}. YEAR = {2023}}

Generative AI has seen remarkable growth over the past few years, with diffusion models being state-of-the-art for image generation. This study investigates the use of diffusion models in artificial data generation for electronic circuits to enhance the accuracy of subsequent machine learning models in tasks such as performance assessment, design, and testing when training data is usually known to be very limited. We utilize simulations in the HSPICE design environment with 22nm CMOS technology nodes to obtain representative real training data for our proposed diffusion model. Our results demonstrate the close resemblance of synthetic data using diffusion models to real data. We validate the quality of generated data and demonstrate that data augmentation is certainly effective in the predictive analysis of VLSI design for digital circuits.

@inproceedings{bib_A_7__2023, AUTHOR = {ALI, HULUVALLAY MOHAMMED ASHFAKH and Abhishek, P V and Jain, Arpan and D, Naveen and Abbas, Zia and Hamed, Ehab A. and Lee, Inhee }, TITLE = {A 7 nW, 1 kHz,− 40–170° C Relaxation Oscillator with Switch-Leakage Compensation for Low-Power High-Temperature IoT Systems}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2023}}

This paper proposes a low-power relaxation oscillator for low-power high-temperature IoT systems. It generates a 959 Hz clock signal from −40 to 170°C, consuming 6.75 nW at 0.65 V. A proposed switch-leakage compensation scheme nullifies the effects of body diode and subthreshold leakages on oscillator output frequency at high temperatures, thereby obtaining a wide operating temperature range. The oscillator implemented in a 180 nm CMOS process achieves a temperature coefficient of 40 ppm/°C from −40 to 170 °C at 0.65 V and a line sensitivity of 0.5 %/V from 0.65 to 2.4 V at room temperature, in simulation. Compared with state-of-the-art sub- μW oscillators, this circuit obtains the highest operating temperature and the maximum temperature range.

@inproceedings{bib_A_Hi_2023, AUTHOR = {Pathy, Ashutosh and Zahra, Andleeb and Ahmad, Amir and Abbas, Zia }, TITLE = {A High PSRR CMOS Voltage and Current Reference in One Circuit Without Amplifier for Low Power Applications}, BOOKTITLE = {International Conference on Microelectronics}. YEAR = {2023}}

This paper presents a low power voltage reference and current reference in one circuit. The reference voltage is the sum of the complementary to absolute temperature (CTAT) gatesource voltage of a MOSFET operating in the subthreshold region and a scaled version of the proportional to absolute temperature (PTAT) ΔVGS of two MOSFETs operating in subthreshold region. The generated temperature independent reference current is the ratio of the reference voltage and a resistance. The proposed circuit does not use an operational transconductance amplifier (OTA) to generate the reference current, thereby eliminates the variation in current due to any offset of the OTA. Furthermore, the circuit uses a native MOSFET for ameliorating the DC PSRR. The proposed circuit is designed in a 130nm CMOS process. The circuit works with a minimum supply voltage of 1.2V while generating a reference voltage of around 0.7V and a reference current of around 100nA. A TC of 100 ppm/˚C for the reference voltage and a TC of 108 ppm/˚C for the reference current are noted for mismatch and process variations from Monte-Carlo simulations for 300 samples. The circuit consumes only 240nW of power, which makes it suitable for ultra-low power applications.

@inproceedings{bib_A_0._2023, AUTHOR = {Mittal, Chetan and Dey, Arnab and Banerjee, Anubhab and ALI, HULUVALLAY MOHAMMED ASHFAKH and Abbas, Zia }, TITLE = {A 0.85V, 593pA, Trim-free Duty-cycled Current Reference for Ultra-Low Power IoT Applications}, BOOKTITLE = {International Conference on VLSI Design}. YEAR = {2023}}

—This paper presents a sub-1V, 593 pA current reference without using resistors and amplifiers. Temperature compensation is achieved by incorporating a CTAT gate to source voltage and a PTAT drain to source voltage in an NMOSbased sub-threshold biased circuit. The proposed architecture achieves ± 3σ/µ process variation of ± 0.75%, which enables seamless trim-free operation. Implemented in the 90nm CMOS process, the temperature-compensated current reference achieves a temperature coefficient of 378 ppm/oC over a high-temperature range of -40 to 100 oC and a line sensitivity of 0.198%/V in a supply voltage range from 0.8 to 2.5 V. Duty cycling technique is adopted in the CTAT generator to reduce the total average power consumption. The proposed circuit occupies an area of 0.074 mm2 while consuming only 3.3 nW at a typical corner of 27 oC and 0.8 V supply.

@inproceedings{bib_A_37_2023, AUTHOR = {Mittal, Chetan and Dey, Arnab and ALI, HULUVALLAY MOHAMMED ASHFAKH and Le, Khanh M and Abbas, Zia }, TITLE = {A 37nW, All-in-One Trim-free Voltage/Current Reference without using Resistors and Amplifiers}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2023}}

This paper presents a trim-free, low-power, and high-precision voltage/current reference for IoT and biomedical applications. The voltage reference is generated by the proper addition of CTAT and PTAT voltages, whereas, the current reference is generated using a MOSFET in the active region, which acts like a resistor and helps in lowering power consumption without increasing the form factor. Implemented in the 90nm CMOS process, the proposed voltage/current reference outputs a voltage and current of 820mV and 3.23nA, respectively. Without trimming, the process variation of the proposed voltage/current reference is 1.34%(σ/μ) / 1.75%(σ/μ) and the temperature coefficient of the voltage/current reference is 62ppm/oC / 332ppm/oC over the temperature range of -40oC to 100oC. The line sensitivity of the voltage/current reference is 0.296%/V / 0.414%/V for a wide supply range of 1V - 3.5V. The area occupied by the total circuit is 0.0112mm2, while the total power consumption of the design is 37nW at the typical corner of 27oC and 1V supply.

@inproceedings{bib_Enha_2023, AUTHOR = {Srivastava, Prasha and Kumar, Pawan and Abbas, Zia }, TITLE = {Enhancing ML model accuracy for Digital VLSI circuits using diffusion models: A study on synthetic data generation}, BOOKTITLE = {Technical Report}. YEAR = {2023}}

Generative AI has seen remarkable growth over the past few years, with diffusion models being state-of-the-art for image generation. This study investigates the use of diffusion models in generating artificial data generation for electronic circuits for enhancing the accuracy of subsequent machine learning models in tasks such as performance assessment, design, and testing when training data is usually known to be very limited. We utilize simulations in the HSPICE design environment with 22nm CMOS technology nodes to obtain representative real training data for our proposed diffusion model. Our results demonstrate the close resemblance of synthetic data using diffusion model to real data. We validate the quality of generated data, and demonstrate that data augmentation certainly effective in predictive analysis of VLSI design for digital circuits.

@inproceedings{bib_A_16_2023, AUTHOR = {Dey, Arnab and Lee, Inhee and Ali, Ashfakh and Jain, Arpan and Pullela, Abhishek and Abbas, Zia }, TITLE = {A 162nW, 0.845 pJ/step Resistance-to-Digital Converter for Miniature Battery-Powered Sensing Systems}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2023}}

This paper proposes a 162nW resistance-to-digital converter (RDC) for miniature battery-powered sensing systems. The RDC first converts input resistance to a pulse by charging a capacitor to a threshold voltage with a current proportional to the resistance. It compensates temperature sensitivity of the charging current by generating the threshold voltage with the same temperature dependency. Then, the circuit digitizes the pulse using an up-down counter that cancels temperature-dependent delay and offset of the low-power comparator in a digital Correlated Double Sampling (CDS) style. Designed in a 180 nm CMOS process, the proposed circuit achieves a figure-of-merit (FoM) of 0.845pJ/c.s. in simulation, with a conversion time of 50 ms for input resistance from to , while consuming 162nW at a supply voltage of 900 mV. Also, it obtains a temperature sensitivity of 26.9ppm/°C from −40 to 100°C

@inproceedings{bib_An_1_2023, AUTHOR = {Agarwal, Samriddhi and Yerragudi, Shameer Basha and D, Naveen and Lee, Inhee and Abbas, Zia }, TITLE = {An 18.5nW, 62.9dB PSRR, Switched-Capacitor Bandgap Voltage Reference using Low Power Clock Generator Circuit for Biomedical Applications}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2023}}

This paper proposes a switched-capacitor network (SCN) based fractional bandgap voltage reference (BGR) circuit designed in 180nm CMOS process to achieve high accuracy and low power consumption for implantable biomedical applications. The design proposes a VEB generator that employs a 2x charge pump and an improved SCN to generate a temperature inde-pendent reference voltage (VREF) ’. A low-power clock generator circuit is proposed, which reduces the leakage current by 37 % compared to previous works, thereby reducing the circuit's power consumption to 18.5nW at typical conditions. The design works from a supply voltage of 0.5V and has a TC of 74. Sppm/ ∘C over a temperature range of 0−80∘C . The PSRR of the circuit is -62.9dB at 100Hz. Based on the Monte Carlo simulations of 500 samples, we obtain an untrimmed 3σ/μ of 2.6%. The design occupies an active area of 0.027mm

@inproceedings{bib_Desi_2023, AUTHOR = {Chatterjee, Srayan Sankar and Sahni, Arpit and Harikrishna, Kambham and Abbas, Zia and Srivastava, Abhishek }, TITLE = {Design and Analysis of Low Power 20 GHz Colpitts VCO with FoM of 196.26 dBc/Hz}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2023}}

This work introduces an ultra low power gm-boosted Colpitts voltage controlled oscillator (VCO) with a transformer based tank operating near 20 GHz. The proposed VCO is implemented in TSMC 65 nm CMOS technology. Through postlayout simulations, it is demonstrated that the proposed VCO exhibits a remarkable figure-of-merit of 196.26 dBc/Hz and achieves a phase noise of -111.21 dBc/Hz at a 1 MHz offset while operating at 19.6 GHz. Additionally, the VCO provides a tuning range of 1.7 GHz (18 - 19.7 GHz) and consumes only 1.2 mW of power from a 1 V supply.

@inproceedings{bib_A_0._2023, AUTHOR = {, and Sahishnavi, Bhartipudi and Raghava, I Sri Sampath Kumar and ALI, HULUVALLAY MOHAMMED ASHFAKH and Dey, Arnab and Lee, Inhee and Abbas, Zia }, TITLE = {A 0.5 V, pico-watt, 0.06%/V/0.03%/V low supply sensitive current/voltage reference without using amplifiers and resistors}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2023}}

The paper presents a 0.5V supply, gate leakage-based current/voltage reference for ultra-low power IoT and biomedical applications. The references are generated by the proper addition of PTAT and CTAT curves, which are obtained by exploiting the traditional architecture of the beta multiplier and using the body biasing effect. Gate leakage transistors replace the resistors to ensure low power and low area. The circuit doesn't involve any Op-Amps avoiding the issues of offset that are prominent in these circuits. Implemented in CMOS 90nm technology, the proposed current (voltage) reference achieves a typical accuracy of 34.6ppm/∘C(29.68ppm/∘C) over a wide temperature range of −55∘C to 75∘C with typical value 63.32pA(0.35V). Excellent line sensitivity of 0.0318%N and 0.0576%N are observed for voltage and current reference, respectively, in a supply range of 0.5V - 2.3V. The area occupied by the total circuit is 0.0096mm2, while the power consumption is 415pW at the typical corner of 27∘C and 0.5V supply.

@inproceedings{bib_A_25_2023, AUTHOR = {Vajrala, Abhinav and Akula, Dheekshith Kumar and Dey, Arnab and Abbas, Zia and Le, Khanh M }, TITLE = {A 250pA, Gate-Leakage Based Trimming Free Current Reference, From -55$^oC$ to 150$^oC$ For Lower Power IoT Applications}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2023}}

This paper presents a fully integrated ultra- low power trim-free current reference for wide-temperature applications. The proposed circuit doesn’t incorporate resistors, amplifiers, and start-up circuitry. A sub-threshold current-based curvature compensation is utilized to extend the temperature range. A process calibration technique is included to calibrate against process variations. Designed in a 55nm CMOS process for a temperature range of -55◦C to 150◦C, the current reference occupies an active area of 0.00458mm2. It achieves a line sensitivity of 0.06%/V for a supply range of 1.2-3.6V. The current produced is 250pA, with a temperature coefficient of 70ppm/oC at the typical corner.

@inproceedings{bib_A_2._2023, AUTHOR = {Dey, Arnab and S, Bharadwaj and ALI, HULUVALLAY MOHAMMED ASHFAKH and Sahishnavi, Bhartipudi and Pullela, Abhishek and Abbas, Zia }, TITLE = {A 2.3nW Gate-Leakage Based Sub-Bandgap Voltage Reference with Line Sensitivity of 0.0066%/V from −40°C to 150°C for Low-Power IoT Systems.}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2023}}

The paper presents a novel nW range gate-leakage-based Sub-Bandgap Voltage Reference (sub-BGR) for low-power and high-temperature range IoT applications. It generates a reference voltage of 336mV without incorporating any resistors and operating for a high-temperature range of −40°C to 150°C and a supply range of 0.7V-4V. In the above temperature and supply ranges, the proposed circuit's power consumption only goes up by 30x and 1.025x times, respectively. Designed in a 65nm CMOS process, the proposed architecture achieves an accuracy of 94ppm/°C. It achieves a line sensitivity of 0.0066%/V for a supply range of 0.7V to 4V and a PSRR of 89dB at DC and 1V supply. The proposed circuit shows a±3σ -inaccuracy of 4.295% without additional trimming circuits. It occupies only 0.0851mm2 area while consuming only 2.3nW at 27°C and 21.74nW at 150°C for a 0.7V supply.

@inproceedings{bib_PROP_2023, AUTHOR = {Abbas, Zia and Abhishek, P V and ALI, HULUVALLAY MOHAMMED ASHFAKH and Jain, Arpan }, TITLE = {PROPORTIONAL TO ABSOLUTE TEMPERATURE (PTAT) VOLTAGE GENERATING CIRCUIT FOR GENERATING A PTAT VOLTAGE AND ACTS AS A TEMPERATURE SENSOR}, BOOKTITLE = {United States Patent}. YEAR = {2023}}

A proportional to-absolute-temperature (PTAT) voltage generating circuit connected between a power supply voltage source and a ground for providing a PTAT voltage at an output terminal of the PTAT voltage generating circuit to act as a temperature sensor is provided. The PTAT voltage generating circuit includes a plurality of PMOS transistors. The plurality of PMOS transistors generates a second PTAT voltage by multiplying a first PTAT voltage by a factor equal to a ratio of a first equivalent resistance (R2) and a second resistance (R1) of a first PMOS transistor (M4). The first equivalent resistance (R2) is obtained from a series combination of the plurality of PMOS transistors. The first PTAT voltage is generated by determining a difference between a base-emitter voltage of a first PNP transistor (T1) and the second PNP transistor

@inproceedings{bib_Desi_2023, AUTHOR = {De, Koushik and Le, Khanh Minh and AMURU, DEEPTHI and Abbas, Zia }, TITLE = {Design and fabrication methods of runtime self-tuning analog integrated circuits using machine learning}, BOOKTITLE = {United States Patent}. YEAR = {2023}}

An Integrated Circuit with an automatically re-tuning analog circuit is provided. The Integrated Circuit comprises (a) an analog circuit comprising a plurality of tunable components each configured to respond to a plurality of change control bits, (b) a Process, Voltage Temperature (PVT) characteristics monitor comprising a plurality of PVT sensors, (c) a tuning memory embedded with a machine learning (ML) model of the analog circuit and (d) an artificial intelligence (AI) engine configured to receive a PVT signal input from the plurality of PVT sensors and the machine learning model embedded in the tuning memory. Each tunable component is configured to change its electrical characteristics such that together each of the tunable components is enabled to retune the analog circuit to attain a predefined set of electrical characteristics.

@inproceedings{bib_AI/M_2023, AUTHOR = {AMURU, DEEPTHI and Vudumula, Harsha V. and Reddy, Cherupally Pavan Kalyan and Reddy, Gurram Sushanth and Ahmad, Amir and Zahra, Dr. Andleeb and Abbas, Zia }, TITLE = {AI/ML algorithms and applications in VLSI design and technology}, BOOKTITLE = {Integration}. YEAR = {2023}}

An evident challenge ahead for the integrated circuit (IC) industry is the investigation and development of methods to reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual, timeconsuming, and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-largescale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past toward VLSI design and manufacturing. Moreover, we discuss the future scope of AI/ML applications to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations.

@inproceedings{bib_Appr_2023, AUTHOR = {Ahmed, Mohammed Salman and Kalesha, Md and Zahra, Dr. Andleeb and Abbas, Zia }, TITLE = {Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture}, BOOKTITLE = {Integration}. YEAR = {2023}}

Approximate Computing techniques are finding a central role in modern applications, by optimizing architectures to relax some computation but with a constrained inaccuracy. In many applications, the FFT algorithm is invariably applied and there is a need for approximate low energy hardware solutions to the FFT. The paper thus proposes an approximate, fixed-point, in-place, shared memory architecture for FFT. It is well observed that the energy at FFT I/Os is not strictly contiguous, hence the proposed FFT exploits this window to tune the error. The proposed FFT and its associated butterfly unit is constructed to efficiently incorporate approximate Toom–Cook multiplication. As said, a supporting function in error correction based on the sparsity patterns, is a feature of this design. The design synthesized at 32 n m shows on average, a 48.6% and 52.8% improvement in consumption of area and energy, respectively …

@inproceedings{bib_Qual_2023, AUTHOR = {Srivastava, Prasha and Kumar, Pawan and Abbas, Zia }, TITLE = {Qualitative Data Augmentation for Performance Prediction in VLSI Circuits}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2023}}

Various studies have shown the advantages of using Machine Learning (ML) techniques for analog and digital IC design automation and optimization. Data scarcity is still an issue for electronic designs, while training highly accurate ML models. This work proposes generating and evaluating artificial data using generative adversarial networks (GANs) for circuit data to aid and improve the accuracy of ML models trained with a small training data set. The training data is obtained by various simulations in the Cadence Virtuoso, HSPICE, and Microcap design environment with TSMC 180nm and 22nm CMOS technology nodes. The artificial data is generated and tested for an appropriate set of analog and digital circuits. The experimental results show that the proposed artificial data generation significantly improves ML models and reduces the percentage error by more than 50% of the original percentage error, which were previously trained with insufficient data. Furthermore, this research aims to contribute to the extensive application of AI/ML in the field of VLSI design and technology by relieving the training data availability-related challenges.

@inproceedings{bib_Fast_2022, AUTHOR = {Agarwal, Kushagra and Jain, Aryamaan and AMURU, DEEPTHI and Abbas, Zia }, TITLE = {Fast and efficient ResNN and Genetic optimization for PVT aware performance enhancement in digital circuits}, BOOKTITLE = {International Symposium on VLSI Design, Automation and Test}. YEAR = {2022}}

This paper presents a fast and efficient optimization engine with multi-directional, multi-objective algorithms based on a robust transistor sizing approach to improve digital circuit performance. However, such optimization processes are highly simulator-dependent and computationally expensive tasks. There-fore, we propose developing machine learning-based reliable models considering process and operating variations to speed up the optimization procedure by running them on developed Residual Neural Network (ResNN) models instead of running expensive circuit simulations. Results on 22nm Metal Gate High-K digital cells show a reduction in delay and leakage up to 36.7% and 18.8 %, respectively improving computational efficiency by several orders.

@inproceedings{bib_Inve_2022, AUTHOR = {Fatema, Anis and Kuriakose, Ivin and Devendra, Deeksha and Abbas, Zia }, TITLE = {Investigation of the Mechanical Reliability of a Velostat-based Flexible Pressure Sensor}, BOOKTITLE = {IEEE International Conference on Flexible and Printable Sensors and Systems}. YEAR = {2022}}

The technological advancements in healthcare mon- itoring devices, automation, consumer electronics, and soft robotics have resulted in extensive research in flexible pressure, force, and tactile sensors. Piezoresistive sensors are the most widely used flexible pressure sensors due to their low-cost fabrication, high flexibility and simple data-acquisition circuits. In this paper, we report the bending response of a velostat- based flexible pressure sensor by examining its reliability when subjected to repeated mechanical stress. The observed deviation in output voltage was 0.95% for 15 mm, 0.95% for 20 mm, 0.97% for 25 mm, and 2.2% for 30 mm bending radii, for 150 bending cycles, with respect to the flat position. We present a two-parameter (a, b) calibration for the pressure sensor with a fixed bias resistance in the readout circuit. This model can be used to further minimize the deviation due to bending cycles. The results obtained from the experimental research have shown a practical possibility of implementing velostat-based sensors for both static and dynamic flexible systems. Index Terms—Reliability; piezoresistive; pressure sensor; me- chanical stress; velostat

@inproceedings{bib_A_18_2022, AUTHOR = {Jain, Arpan and Abhishek, P V and ALI, HULUVALLAY MOHAMMED ASHFAKH and Abbas, Zia }, TITLE = {A 180o Phase Shift Biasing Technique for Realizing High PSRR in Low Power Temperature Sensors}, BOOKTITLE = {International Conference on VLSI Design}. YEAR = {2022}}

The paper presents a low-cost method (no extra LDO, Op-amp) to increase the PSRR of composite pair based temperature sensor. Composite pair is a commonly used circuit to generate a linear PTAT voltage for a wide temperature range. A 180° phase shift, voltage biasing technique is introduced at the gate of the NMOS transistor to obtain a supply independent bias current in composite pair. The proposed technique thus achieves a high supply noise rejection. The circuit as a whole does not require additional circuitry, therefore it saves power and area. A 6μW Temperature sensor with 1mV/°c slope is designed in TSMC 180nm technology and achieves PSRR of -80dB. Post-layout simulation results show that the temperature sensor achieves inaccuracy of ±0.1°C from −55°C to 125°C, PSRR of −80dB at 105Hz and -70dB at 200kHz at 1V power supply, and the line regulation of 0.016%/V in a supply voltage range of 1V to 2.5V. Monte-Carlo simulation result for the output PSRR shows −80.56dB as the mean-value with a maximum deviation of ±1.5dB.

@inproceedings{bib_A_15_2022, AUTHOR = {Abhishek, P V and ALI, HULUVALLAY MOHAMMED ASHFAKH and Jain, Arpan and Lee, Inhee and Abbas, Zia }, TITLE = {A 156pW Gate-Leakage Based Voltage/Current Reference for Low-Power IoT Systems}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2022}}

The paper presents a sub-nW gate-leakage based voltage and current reference in a single circuit whose reference values are scalable and doesn’t incorporate start-up circuits or resistors in the architecture. The power consumption of the proposed circuit increases by only 2.1x in the temperature range of -55°C to 100°C, unlike conventional voltage/current references where the power consumption increases exponentially w.r.t temperature. Implemented in 90nm technology, the proposed voltage reference (current reference) achieves post-trim typical accuracy of 22ppm/°C(58ppm/°C) and worst-case accuracy of 71ppm/°C(78ppm/°C). Excellent line sensitivities of 0.029%/V and 0.059%/V are observed for voltage and current reference respectively, in a supply range of 1V - 3V. Without any start-up circuit, the observed 99% settling times for voltage and current reference are 1.92ms and 2.526ms respectively. The area occupied by the total circuit is 0.0015mm 2 , while the power consumption is 156pW at typical corner, 27°C and 1V supply.

@inproceedings{bib_A_9._2022, AUTHOR = {Agarwal, Samriddhi and Pathy, Ashutosh and Abbas, Zia }, TITLE = {A 9.5nW, 0.55V Supply, CMOS Current Reference for Low Power Biomedical Applications}, BOOKTITLE = {IEEE Transactions on Circuits and Systems II: Express Briefs}. YEAR = {2022}}

This brief proposes an ultra-low-power current ref- erence in TSMC 180nm technology. Temperature compensation is achieved by taking the ratio of compensated voltage and an on-chip resistance. This design uses the concept of the back- gate effect of critical MOSFET to generate complementary to absolute temperature (CTAT) voltage. The circuit works from a supply voltage of 0.55V and is designed for a reference current of 5.6nA. Furthermore, a pseudo-differential amplifier (PD-AMP) helps realize low line regulation of 0.022%/V in the supply range of 0.55 to 1.9V. An average temperature coefficient (TC) of 256.07ppm/◦C is achieved for mismatch and process variations in Monte-Carlo simulations for 1000 samples over a tempera- ture range of −30◦C to 70◦C. The circuit consumes only 9.5nW of power (at room temperature and minimum supply voltage), making it suitable for ultra-low-power biomedical applications. Index Terms—Peaking current reference, biomedical, sub- threshold region, DIBL, PD-AMP.

@inproceedings{bib_AI-d_2022, AUTHOR = {Le, Khanh M and De, Koushik and AMURU, DEEPTHI and Abbas, Zia }, TITLE = {AI-driven self adapting microelectronic circuits}, BOOKTITLE = {United States Patent}. YEAR = {2022}}

The present description relates to a method based on artifi cial intelligence to implement a wide range of microelec tronic circuits that can adapt by themselves to the usage conditions ( e.g. loading changes ) , manufacturing variances or defects ( e.g. process variations , device parameter mis matches , device model inaccuracies or changes , etc. ) , as well as environmental conditions ( e.g. voltage , temperature , interference ) in order to negate all or part of their effects on the circuit performance characteristics and achieve a very tight set of specifications over the wide range of conditions . Each microelectronic circuit is represented by a neural network model whose behavior is a function of the actual input signals , the usage and environmental conditions . An attached AI engine will infer from the model , the input signals , the usage conditions and the environmental condi tions and create the adaptive changes required to modify the microelectronic circuit's behavior to negate all or part of their effects on the circuit performance characteristics and to achieve a very tight set of specifications .

@inproceedings{bib_An_E_2022, AUTHOR = {Ullah, Hadaate and Heyat, Md Belal Bin and Akhtar, Faijan and Muaad, Abdullah Y and Islam, Md and Abbas, Zia and Pan, Taisong and Gao, Min and Lin, Yuan }, TITLE = {An End-to-End Cardiac Arrhythmia Recognition Method with an Effective DenseNet Model on Imbalanced Datasets Using ECG Signal}, BOOKTITLE = {Computational Intelligence and Neuroscience}. YEAR = {2022}}

Electrocardiography (ECG) is a well-known noninvasive technique in medical science that provides information about the heart’s rhythm and current conditions. Automatic ECG arrhythmia diagnosis relieves doctors’ workload and improves diagnosis effectiveness and efficiency. This study proposes an automatic end-to-end 2D CNN (two-dimensional convolution neural networks) deep learning method with an effective DenseNet model for addressing arrhythmias recognition. To begin, the proposed model is trained and evaluated on the 97720 and 141404 beat images extracted from the Massachusetts Institute of Technology-Beth Israel Hospital (MIT-BIH) arrhythmia and St. Petersburg Institute of Cardiological Technics (INCART) datasets (both are imbalanced class datasets) using a stratified 5-fold evaluation strategy. The data is classified into four groups: N (normal), V (ventricular ectopic), S (supraventricular ectopic), and F (fusion), based on the Association for the Advancement of Medical Instrumentation® (AAMI). The experimental results show that the proposed model outperforms state-of-the-art models for recognizing arrhythmias, with the accuracy of 99.80% and 99.63%, precision of 98.34% and 98.94%, and F1-score of 98.91% and 98.91% on the MIT-BIH arrhythmia and INCART datasets, respectively. Using a transfer learning mechanism, the proposed model is also evaluated with only five individuals of supraventricular MIT-BIH arrhythmia and five individuals of European ST-T datasets (both of which are also class imbalanced) and achieved satisfactory results. So, the proposed model is more generalized and could be a prosperous …

@inproceedings{bib_Ther_2022, AUTHOR = {Zahra, Dr. Andleeb and Cesare, Giampiero De and Caputo, Domenico and Abbas, Zia }, TITLE = {Thermal Study of Thin-Film Heater for PCR Reaction-Based Applications}, BOOKTITLE = {Microactuators, Microsensors and Micromechanisms:}. YEAR = {2022}}

This paper presents the design, fabrication, and characterization of a thin-film Cr-Al-Cr (300 A°-1500 A°-300 A°) metal stack heater specially designed for chemical reactions which occur at a uniform temperature in the lab on a chip platform such as polymerase chain reaction (PCR) applications. The heater has been designed using COMSOL Multiphysics. The simulated design has been fabricated using lithography and patterning on a 5 × 5 cm2 glass substrate. For the validation of the proposed design thermal study of the fabricated heater has also been done using a FLIR IR camera. A very good agreement between the thermal image of modeled and fabricated heater has been achieved. This demonstrates the suitability of the proposed heater for PCR reaction applications.

@inproceedings{bib_2022_2022, AUTHOR = {Abbas, Zia and Abdekhoda, and J, and Abdelfattah, and S., and Abdelrahman, and D, and Abdollahi, and B, and Abdollahi, and B, and Abich, and Abou-Khousa, and Aboushady, and H, }, TITLE = {2022 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 69}, BOOKTITLE = {IEEE Transactions on Circuits and Systems II: Express Briefs}. YEAR = {2022}}

This index covers all technical items—papers, correspondence, reviews, etc.—that appeared in this periodical during 2022, and items from previous years that were commented upon or corrected in 2022. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author’s name. The primary entry includes the coauthors’ names, the title of the paper or other item, and its location, specified by the publication abbrevia- tion, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author’s name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index.

@inproceedings{bib_A_No_2022, AUTHOR = {Pal, Rishi and Adhikari, Deepak and Heyat, Md Belal Bin and Heyat, Md Belal Bin and Lipari, Vivian and Ballester, Julien Brito and Díez, Isabel De La Torre and Abbas, Zia and , Dakun Lai and , Dakun Lai }, TITLE = {A Novel Smart Belt for Anxiety Detection, Classification, and Reduction Using IIoMT on Students’ Cardiac Signal and MSY}, BOOKTITLE = {Bioengineering}. YEAR = {2022}}

A Novel Smart Belt for Anxiety Detection, Classification, and Reduction Using IIoMT on Students’ Cardiac Signal and MSY

@inproceedings{bib_Syst_2022, AUTHOR = {Abbas, Zia and De, Koushik }, TITLE = {System and method for analog design synthesis using analog cell component library based on ai/ml}, BOOKTITLE = {United States Patent}. YEAR = {2022}}

A system and method for synthesizing analog design in real - time using an artificial intelligence and machine learn ing ( AI / ML ) model are provided . The method includes ( i ) generating a behavioral model of an analog macro using the AI / ML model ; ( ii ) determining one or more operations that is required to implement the behavioral model by scanning the behavioral model ; ( iii ) selecting , using the AI / ML model , the analog macro based on at least one specification that corresponds to the analog macro ; ( iv ) synthesizing , the analog macro that is selected by the AI / ML model 214 and one or more leaf cells for each selected analog macro of the behavioral architectural implementation to obtain a gate level circuit design based on a figure of merit ( FoM ) of the analog macro and ( v ) determining , using the AI / ML model , the analog circuit design for the integrated circuit system based on the gate level circuit design that is synthesized .

@inproceedings{bib_Fast_2022, AUTHOR = {Agarwal, Kushagra and Jain, Aryamaan and Amuru, Deepthi and Abbas, Zia }, TITLE = {Fast and efficient ResNN and Genetic optimization for PVT aware performance enhancement in digital circuits}, BOOKTITLE = {International Symposium on VLSI Design, Automation and Test}. YEAR = {2022}}

This paper presents a fast and efficient optimization engine with multi-directional, multi-objective algorithms based on a robust transistor sizing approach to improve digital circuit performance. However, such optimization processes are highly simulator-dependent and computationally expensive tasks. Therefore, we propose developing machine learning-based reliable models considering process and operating variations to speed up the optimization procedure by running them on developed Residual Neural Network (ResNN) models instead of running expensive circuit simulations. Results on 22nm Metal Gate HighK digital cells show a reduction in delay and leakage up to 36.7% and 18.8%, respectively improving computational efficiency by several orders.

@inproceedings{bib_AI/M_2022, AUTHOR = {Amuru, Deepthi and Vudumula, Harsha V and Cherupally, Pavan K and Gurram, Sushanth R and Ahmad, Amir and Zahra, Andleeb and Abbas, Zia }, TITLE = {AI/ML Algorithms and Applications in VLSI Design and Technology}, BOOKTITLE = {Technical Report}. YEAR = {2022}}

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and dataintensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations.

@inproceedings{bib_Impl_2022, AUTHOR = {Kamadi, Annapurna and Abbas, Zia }, TITLE = {Implementation of TRNG with SHA-3 for hardware security}, BOOKTITLE = {Microelectronic Journal}. YEAR = {2022}}

Random Number Generators (RNGs) are the solution for cryptographic applications to enhance hardware security. These RNGs ought to have three specific properties unpredictability, aperiodic, and good statistical criteria. This brief presents a True Random Number Generator (TRNG) based on Ring oscillators’ jitter with MLFSR. The MLFSR is augmented with a set of prime primitive polynomials, Boolean, and non-linear functions to attain a non-linear, unpredictable, and extended sequence period. Paper mainly focused on achieving high randomness by integrated the TRNG with a new promising crypto engine Keccak as a post-processing block; leads to extensively more security in data transfer, encryption keys, data authenticity of ICs, and IoT based applications. The RNG design is coded in Verilog HDL and implemented on the FPGA Zed board. Hashing is performed with a throughput of 2.4Gbps at 100 MHz either with RNG data or SHA data. Evaluated the randomness of the generated non-deterministic bitstreams (10 Mb) using the NIST 800–22 & Diehard test suite and successfully passed.

@inproceedings{bib_A_41_2021, AUTHOR = {Pullela, Abhishek and ALI, HULUVALLAY MOHAMMED ASHFAKH and Jain, Arpan and Banthi, Adithya and Abbas, Zia }, TITLE = {A 419PW process-invariant temperature sensor for ultra-low power microsystems}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2021}}

The paper presents a sub-nW BJT based temperature sensor for ultra-low power microsystems. The sensor is based on amplifying the difference between base-emitter voltages of BJTs using gate-leakage transistors. Implemented in UMC 65nm technology, the sensor occupies an area of 0.005mm 2 . It achieves a maximum non-linearity error of 0.12 o C(3σ) over the temperature range of - 55 o C to 80 o C. Without any trimming, a worst case inaccuracy of +0.36 o C/ - 1.61 o C is observed w.r.t process variations, depicting the process-invariant nature of the temperature sensor. It also achieves a low supply sensitivity of 0.56 o C/V over a wide supply range of 0.7V-3V. The power consumption of the sensor is 419pW at 27 o C and 0.7V supply.

@inproceedings{bib_A_44_2021, AUTHOR = {Pullela, Abhishek and ALI, HULUVALLAY MOHAMMED ASHFAKH and Reddy, Gurram Sushanth and Jain, Arpan and Abbas, Zia }, TITLE = {A 443pW Accumulation-Mode Gate-Leakage Based Bandgap Reference for IoT Applications}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2021}}

The paper presents a sub-nW bandgap reference (BGR) that exploits the temperature variation of gate-leakage current in thin oxide devices operating in the accumulation region to generate the reference voltage. The incorporation of gateleakage transistors scales down the power consumption of the BGR to pico-watt level without using any large physical resistors or sophisticated techniques, thereby making it suitable for IoT applications. The BGR is designed in TSMC 65nm technology and occupies an area of 0.009mm 2 . Post layout simulation results show nominal and worst-case accuracies of 23ppm/°C and 44ppm/°C respectively in the temperature range of -40°C to 100°C. Without any trimming, an inaccuracy (±3σ) of 3% is observed for the reference voltage, showing its resilience to process variations. It also exhibits a typical line sensitivity of 0.063%/V in a supply range of 1.5V-3.8V and a PSRR of -65dB at DC and 1.8V supply. The power consumption is observed to be 443pW at 1.5V supply and nominal temperature

@inproceedings{bib_A_0._2021, AUTHOR = {Pathy, Ashutosh and Adithya, Banthi and Abbas, Zia }, TITLE = {A 0.85V Supply, High PSRR CMOS Voltage Reference without Resistor and Amplifier for UltraLow Power Applications}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2021}}

This paper presents an ultra-low power CMOS voltage reference (CVR) which is free of amplifier and resistor. A current generator circuit is used to generate a supply independent current to bias the active load in the temperature compensation circuit. Drain-source voltage of two critical MOSFETs is made equal in the current generator circuit by using a feedback arrangement to ensure a high PSRR of -75dB for the reference voltage. Temperature compensation is achieved by using the complementary to absolute temperature (CTAT) nature of gatesource of a MOSFET operating in the subthreshold region and proportional to absolute temperature (PTAT) nature of conventional composite pair architecture. The proposed CVR is designed in TSMC 180nm technology. The circuit works desirably for a supply range of 0.85V to 2.3V while generating a reference voltage of around 0.68V. Maximum temperature coefficient (TC) of 184 ppm/˚C and minimum TC of 69 ppm/˚C are noted for mismatch and process variations in the Monte-Carlo simulation for 1000 samples. The circuit consumes only 46nW of power, which makes it suitable for ultra-low power applications. Keywords— CMOS voltage reference, Line sensitivity, Subthreshold region, Temperature compensation.

@inproceedings{bib_A_0._2021, AUTHOR = {Pathy, Ashutosh and Adithya, Banthi and Abbas, Zia }, TITLE = {A 0.85 V Supply, High PSRR CMOS Voltage Reference without Resistor and Amplifier for Ultra-Low Power Applications}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2021}}

This paper presents an ultra-low power CMOS voltage reference (CVR) which is free of amplifier and resistor. A current generator circuit is used to generate a supply independent current to bias the active load in the temperature compensation circuit. Drain-source voltage of two critical MOSFETs is made equal in the current generator circuit by using a feedback arrangement to ensure a high PSRR of -75dB for the reference voltage. Temperature compensation is achieved by using the complementary to absolute temperature (CTAT) nature of gatesource of a MOSFET operating in the subthreshold region and proportional to absolute temperature (PTAT) nature of conventional composite pair architecture. The proposed CVR is designed in TSMC 180nm technology. The circuit works desirably for a supply range of 0.85V to 2.3V while generating a reference voltage of around 0.68V. Maximum temperature coefficient (TC) of 184 ppm/˚C and minimum TC of 69 ppm/˚C are noted for mismatch and process variations in the Monte-Carlo simulation for 1000 samples. The circuit consumes only 46nW of power, which makes it suitable for ultra-low power applications.

@inproceedings{bib_AI-d_2021, AUTHOR = {Le, Khanh M and De, Koushik and Amuru, Deepthi and Abbas, Zia }, TITLE = {AI-driven self adapting microelectronic circuits}, BOOKTITLE = {United States Patent}. YEAR = {2021}}

The present description relates to a method based on artifi cial intelligence to implement a wide range of microelec tronic circuits that can adapt by themselves to the usage conditions ( e.g. loading changes ) , manufacturing variances or defects ( e.g. process variations , device parameter mis matches , device model inaccuracies or changes , etc. ) , as well as environmental conditions ( e.g. voltage , temperature , interference ) in order to negate all or part of their effects on the circuit performance characteristics and achieve a very tight set of specifications over the wide range of conditions . Each microelectronic circuit is represented by a neural network model whose behavior is a function of the actual input signals , the usage and environmental conditions . An attached AI engine will infer from the model , the input signals , the usage conditions and the environmental condi tions and create the adaptive changes required to modify the microelectronic circuit's behavior to negate all or part of their effects on the circuit performance characteristics and to achieve a very tight set of specifications

@inproceedings{bib_A_44_2021, AUTHOR = {Pullela, Abhishek and ALI, HULUVALLAY MOHAMMED ASHFAKH and Reddy, Gurram Sushanth and Jain, Arpan and Abbas, Zia }, TITLE = {A 443pW Accumulation-Mode Gate-Leakage Based Bandgap Reference for IoT Applications}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2021}}

—The paper presents a sub-nW bandgap reference (BGR) that exploits the temperature variation of gate-leakage current in thin oxide devices operating in the accumulation region to generate the reference voltage. The incorporation of gateleakage transistors scales down the power consumption of the BGR to pico-watt level without using any large physical resistors or sophisticated techniques, thereby making it suitable for IoT applications. The BGR is designed in TSMC 65nm technology and occupies an area of 0.009mm2 . Post layout simulation results show nominal and worst-case accuracies of 23ppm/oC and 44ppm/oC respectively in the temperature range of −40oC to 100oC. Without any trimming, an inaccuracy (±3σ) of 3% is observed for the reference voltage, showing its resilience to process variations. It also exhibits a typical line sensitivity of 0.063%/V in a supply range of 1.5V-3.8V and a PSRR of -65dB at DC and 1.8V supply. The power consumption is observed to be 443pW at 1.5V supply and nominal temperature.

@inproceedings{bib_Tran_2021, AUTHOR = {Saha, Prasenjit and Sai, Kalluru Hema and Abbas, Zia }, TITLE = {Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence}, BOOKTITLE = {International Conference on VLSI Design}. YEAR = {2021}}

This paper deals with transistor sizing based static power optimization for multi-stage CMOS circuits using swarm intelligence algorithm. The overall circuit performance is improved by optimizing the individual basic cell performances. Optimized cells are re-used at places with similar circuit scenarios thereby reducing the number of variables to work with. At each stage of execution, the algorithm generates multiple sizing options for basic cells with varying power-delay specifications to choose from. This work proposes a dual sizing approach for critical and non-critical path cells. The overall process has low circuit dependence and has been applied on a wide range of single and multi-stage circuits (including ISCAS benchmark circuits). The approach considers fabrication process parameter variations (for ±3σ design) in addition to a wide range of temperature (-55oC to 125oC) and supply voltage (±10%) variations for robust sizing solutions. Results show leakage reductions up to 63.6%.

@inproceedings{bib_PVT__2021, AUTHOR = {Sai, Kalluru Hema and Saha, Prasenjit and Zahra, Dr. Andleeb and Abbas, Zia }, TITLE = {PVT and Aging Degradation Invariant Automated Optimization Approach for CMOS Low-Power High-Performance VLSI Circuits}, BOOKTITLE = {International Symposium on Quality Electronic Design}. YEAR = {2021}}

In this paper, we aim at optimizing the leakage power and propagation delays using optimization algorithms like Glowworm Swarm Optimization and Neighbourhood Cultivation Genetic Algorithm, subjected to variations in Process, Voltage, Temperature and Aging degradation (PVTA) targeting low power or high performance applications. For high performance applications, we synthesize transistor sizes, at which the critical path delay in worst case PVT conditions with 3 years of NBTI aging degradation is optimized below the critical path delay (of initial sizing) at nominal conditions keeping power budget in bound. On the other hand, for low power applications, we obtain transistor sizing where leakage is reduced by more than 50%, keeping a bound on critical path delay. We have also proposed a step by step optimization method for optimizing complex cells. All the pre and post stress simulations are performed using HSPICE for 22nm Metal Gate High-K dielectric model parameters. The temperature range and the supply voltage ranges are -55 °C to 125 °C and 0.72V to 0.88V respectively. The process parameters are considered at ±3σ variation. The ingenuous working of the circuits for the obtained sizing is ensured by Monte Carlo analysis evaluating over entire range of process variations and operating conditions for the intended life time.

@inproceedings{bib_A_41_2021, AUTHOR = {Abhishek, P V and ALI, HULUVALLAY MOHAMMED ASHFAKH and Jain, Arpan and Banthi, Adithya and Abbas, Zia }, TITLE = {A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Micro systems}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems }. YEAR = {2021}}

The paper presents a sub-nW BJT based temperature sensor for ultra-low power microsystems. The sensor is based on amplifying the difference between base-emitter voltages of BJTs using gate-leakage transistors. Implemented in UMC 65nm technology, the sensor occupies an area of 0.005mm 2 . It achieves a maximum non-linearity error of 0.12°C(3σ) over the temperature range of –55°C to 80°C. Without any trimming, a worst case inaccuracy of +0.36°C/ –1.61°C is observed w.r.t process variations, depicting the process-invariant nature of the temperature sensor. It also achieves a low supply sensitivity of 0.56°C/V over a wide supply range of 0.7V-3V. The power consumption of the sensor is 419pW at 27°C and 0.7V supply.

@inproceedings{bib_Low__2021, AUTHOR = {Saha, Prasenjit and M, Salman Ahmed and Sai, Kalluru Hema and Abbas, Zia }, TITLE = {Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells using Swarm Intelligence}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2021}}

This paper proposes low power optimization using a modified swarm intelligence algorithm for the scenariostransistor sizing based static power reduction and low power standard cell generation for approximate computing. In these scenarios, we explore a lower abstraction level and see how standard cells can be tuned to a power-delay-quality optimal point. For transistor sizing, the algorithm considers fabrication process parameter variations (for ±3σ design) in addition to a wide range of temperature (-55oC to 125oC) and supply voltage (±10%) variations to yield PVT aware robust sizing solutions. The approach has been applied on numerous single and multistage circuits (including ISCAS benchmarks) while proposing a dual sizing solution for non-critical and critical path cells. For approximate systems, we present algorithm-generated full adder designs for speech processing systems. The designs vary in terms of accuracy and power. Results show leakage reductions up to 58.2% for conventional and 66.8% with approximation designs for 22nm metal gate high-K (MGK) technology cells.

@inproceedings{bib_Algo_2021, AUTHOR = {Sai, Kalluru Hema and Saha, Prasenjit and Zahra, Andleeb and Abbas, Zia }, TITLE = {Algorithm driven Power-Timing Optimization Methodology for CMOS Digital Circuits considering PVTA Variations}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2021}}

In this paper, we aim at optimizing the leakage power and propagation delays using optimization algorithms like Glowworm Swarm Optimization and Neighbourhood Cultivation Genetic Algorithm, subjected to variations in Process, Voltage, Temperature and Aging degradation (PVTA) targeting low power or high performance applications. For high performance applications, we synthesize transistor sizes, at which the critical path delay in worst case PVT conditions with 3 years of NBTI aging degradation is optimized below the critical path delay (of initial sizing) at nominal conditions keeping power budget in bound. On the other hand, for low power applications, we obtain transistor sizing where leakage is reduced by more than 50%, keeping a bound on critical path delay. All the pre and post stress simulations are performed using HSPICE for 22nm Metal Gate High-K dielectric model parameters. The temperature range and the supply voltage ranges are −55 °C to 125 °C and 0.72V to 0.88V respectively. The process parameters are considered at ±3σ variation. The ingenuous working of the circuits for the obtained sizing is ensured by Monte Carlo analysis evaluating over entire range of process variations and operating conditions for intended life time.

@inproceedings{bib_A_41_2021, AUTHOR = {Abhishek, P V and ALI, HULUVALLAY MOHAMMED ASHFAKH and Jain, Arpan and Adithya, B and Abbas, Zia }, TITLE = {A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Microsystems}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2021}}

The paper presents a sub-nW BJT based temperature sensor for ultra-low power microsystems. The sensor is based on amplifying the difference between baseemitter voltages of BJTs using gate-leakage transistors. Implemented in UMC 65nm technology, the sensor occupies an area of 0.005mm2 . It achieves a maximum non-linearity error of 0.12oC(3σ) over the temperature range of −55oC to 80oC. Without any trimming, a worst case inaccuracy of +0.36oC/ − 1.61oC is observed w.r.t process variations, depicting the process-invariant nature of the temperature sensor. It also achieves a low supply sensitivity of 0.56oC/V over a wide supply range of 0.7V-3V. The power consumption of the sensor is 419pW at 27oC and 0.7V supply.

@inproceedings{bib_ON-C_2021, AUTHOR = {Jain, Arpan and ALI, HULUVALLAY MOHAMMED ASHFAKH and Abbas, Zia }, TITLE = {ON-CHIP COMPLEMENTARY METAL-OXIDESEMICONDUCTOR (CMOS) RESISTANCE AMPLIFIER}, BOOKTITLE = {INDIAN PATENT}. YEAR = {2021}}

[0002] Resistors are the essential and common elements of any electronic circuits and extensively used in electronic equipment. They are frequently used in Integrated Circuits. The conventional on-chip resistance takes a large silicon area compared to metal oxide 15 semiconductor MOS transistor. In fabrication, the area is proportional to cost. If the silicon area is more, then the cost of the chip also increases. Therefore, large resistances are avoided to fabricate on the chip. For low power circuits, large resistances are often required but due to limited silicon area they are avoided. Hence the conventional resistor is replaced by a complementary metal-oxide-semiconductor CMOS circuit or a switched capacitor-based 20 resistor circuit to save area.

@inproceedings{bib_67pp_2020, AUTHOR = {Yadav, Battu Balaji and Mounika, Kelam and Bathi, Adithya and Abbas, Zia }, TITLE = {67ppm/◦C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems }. YEAR = {2020}}

This work presents a highly accurate current reference of 66nA for ultra-low power applications. A very low figureof-merit (FOM) of 1.3501ppm/◦C 2 is achieved on consuming a minimal quiescent current of 199.37nA. To cancel out process variations, the current subtraction technique is employed and a β-multiplier is used to compensate for mobility (µ) and threshold voltage (Vth). In addition, curvature compensation technique backed by PTAT and CTAT current cancellation is adopted to attain a lower temperature coefficient (TC). Hence, an imperceptible variation of accuracy with temperature and supply variations across all process corners is attained. An adopted trimming scheme further minimizes the overall process spread to ±1.515% without compromising on accuracy. Accordingly, a TC of 67.04ppm/◦C over a wide temperature range of -50◦C to 100◦C is obtained. Furthermore, 1.413%/V line sensitivity (LS) in the supply range of 1.38V to 3V is observed. Low power consumption of 275.13nW@1.38V facilitates its use in high-performance low power applications. Index Terms—FOM, curvature compensation, Line Sensitivity, Proportional to Absolute Temperature (PTAT), Complementary to Absolute Temperature (CTAT), ZTC

@inproceedings{bib_3.75_2020, AUTHOR = {Yadav, Battu Balaji and Abbas, Zia }, TITLE = {3.75ppm/◦C, -91dB PSRR, 27nW, 0.9V PVT Invarian Voltage Reference for Implantable Biomedical Applications}, BOOKTITLE = {International Conference on VLSI Design}. YEAR = {2020}}

This brief presents a CMOS-only ultra low power voltage reference of 0.925V which is designed and simulated in TSMC 180nm technology. Current mixing between SelfBiased Self Cascode MOSFET (SBSCM) and Self Cascode MOSFET (SCM) pair is introduced along with stacking of proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltage generators to get second order curvature compensation. Temperature coefficient (TC) of 3.75ppm/◦C over a wide temperature range of -55◦C to 140◦C is achieved. To feed on the power reduction requirement of low power biomedical applications, the entire circuit is designed in sub-threshold region. Therefore, the total power consumption is 27nW @ 1.45V at room temperature (27◦C). Furthermore, a supply independent current bias aids in realizing high PSRR of -91dB @ 10Hz / -50dB @ 100MHz and line regulation of 0.0779%/V over a supply range 1.45V to 3.6V. Besides, an employed trimming technique attenuates the process spread from ±3% to ±0.3%. Moreover, the proposed design occupies an active area of 0.0054mm2 only. Index Terms—Ultra Low Power, Voltage Reference, PSRR, CTAT, PTAT, Biomedical, SBSCM, SCM.

@inproceedings{bib_3.75_2020, AUTHOR = {Mounika, Kelam and Yadav, Battu Balaji and Abbas, Zia }, TITLE = {3.75ppm/°C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical Applications}, BOOKTITLE = {International Conference on VLSI Design}. YEAR = {2020}}

This brief presents a CMOS-only ultra low power voltage reference of 0.925V which is designed and simulated in TSMC 180nm technology. Current mixing between SelfBiased Self Cascode MOSFET (SBSCM) and Self Cascode MOSFET (SCM) pair is introduced along with stacking of proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltage generators to get second order curvature compensation. Temperature coefficient (TC) of 3.75ppm/°C over a wide temperature range of -55°C to 140°C is achieved. To feed on the power reduction requirement of low power biomedical applications, the entire circuit is designed in sub-threshold region. Therefore, the total power consumption is 27nW @ 1.45V at room temperature (27°C). Furthermore, a supply independent current bias aids in realizing high PSRR of -91dB @ 10Hz / -50dB @ 100MHz and line regulation of 0.0779%/V over a supply range 1.45V to 3.6V. Besides, an employed trimming technique attenuates the process spread from ±3% to ±0.3%. Moreover, the proposed design occupies an active area of 0.0054mm 2 only.

@inproceedings{bib_A_Co_2020, AUTHOR = {Mounika, Kelam and Yadav, Battu Balaji and Abbas, Zia }, TITLE = {A Compact, Power Efficient, Self-Adaptive and PVT Invariant CMOS Relaxation Oscillator}, BOOKTITLE = {Computer Society Annual Symposium on VLSI}. YEAR = {2020}}

This brief presents a novel PVT-invariant CMOS relaxation oscillator for Real-Time Clock (RTC) applications. The proposed design is compatible to work in a low supply voltage domain of SoC. The PVT invariance is achieved by a unique circuit implementation of introducing a self-adaptive mechanism that dynamically modifies the time constant of the oscillator core. Moreover, the design is accompanied by a digital calibration unit for further process compensation. Besides, the introduced supply independent bias circuit has greatly improved the supply regulation of the oscillator frequency. In addition, the design utilizes a complementary to absolute temperature (CTAT) current for temperature compensation. Area efficiency is enhanced by replacing bigger passive device i.e, resistor with an adaptive MOS resistor. The obtained results show that the minimum temperature coefficient (TC) of 31.236ppm/°C is achieved over a range of -40°C to 100°C. The resultant phase noise of -140dBc/Hz@1MHz is observed. The design has achieved a good power efficiency of 1.65nW/KHz at room temperature without a calibration unit. The line sensitivity (LS) of 0.1159%/V is noted in the range of 0.7V to 1.2V. Nevertheless, the entire system occupies an active area of 0.0509mm^2 with a power consumption of 90nW@0.7V. Also, the leakage current of the complete system is <; 54pA. Therefore, the proposed design aims at providing a production-friendly, ease of integration and low-cost solution.

@inproceedings{bib_A_Su_2020, AUTHOR = {ALI, HULUVALLAY MOHAMMED ASHFAKH and Abhishek, P V and Jain, Arpan and Abbas, Zia }, TITLE = {A Sub-nW, 8T Current Reference Consuming Constant Power wrt Process & Temperature}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2020}}

he paper presents an eight transistor (8T) pico-watt current reference with a novel method of rectifying the prob-lem of exponential power increase w.r.t temperature in traditionalsub-nW references. The proposed current reference is obtainedby modifying the traditional beta-multiplier architecture to scale-down the power consumption without sacrificing area. Theconstancy of power consumption w.r.t temperature is achievedby exploiting the voltage-current characteristics of a leakagetransistor in the modified architecture. The proposed currentreference, implemented in UMC 55nm technology, occupies anarea of0.00035mm2. It is designed for a current of 60pA andachieves an accuracy of19ppm/0Cover a wide temperaturerange of−550Cto1250C. The reported line sensitivity for thecurrent reference is 0.07%/V in the supply range of 1.2V - 4V.Post-trim results show a constant power consumption of 144pWw.r.t temperature and process variations @1.2V supply.

@inproceedings{bib_An_E_2020, AUTHOR = {AMURU, DEEPTHI and M, Salman Ahmed and Abbas, Zia }, TITLE = {An Efficient Gradient Boosting Approach for PVT Aware Estimation of Leakage Power and Propagation Delay in CMOS/FinFET Digital Cells}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2020}}

In this paper, we propose an accurate and computationally efficient Gradient Boosting approach for the estimation of statistical variations aware leakage power and propagation delay in the CMOS/FinFET standard digital cells. The proposed model estimates the leakage power and propagation delay w.r.t variations in process, temperature (−55°C to 125°C) and supply voltage(±10% variations). The distinguishing feature of the proposed approach is its compatibility with both CMOS and FinFET technologies. Moreover, the performance of the proposed model is consistent with various technology nodes. Exhaustive tests report an average error of <1% in 16nm CMOS and FinFET standard digital cells w.r.t analog HSPICE simulations with several orders increase in computational speed. Further, the complex cell estimation can be carried out through precharacterized standard cells abstaining longer simulations.

@inproceedings{bib_ATM:_2020, AUTHOR = {M, Salman Ahmed and AMURU, DEEPTHI and Abbas, Zia }, TITLE = {ATM: Approximate Toom-Cook Multiplication for Speech Processing Applications}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2020}}

Approximate Computing has paved way for elaborate savings in design area and latency of modern system architectures processing images or signals, by a deliberate yet tolerable loss of functional accuracy. This paper thus proposes a design of an approximate multiplier based on the efficient Toom-Cook algorithm, that has a lower complexity of O(N logd(zd−1) ) than O(N 2 ), for order d. Inherent integer divisions in the algorithm has restricted its feasibility in hardware, unless without suitable approximation. On an average, the proposed multiplier achieves 53%, 18% and 57% improvements in area, delay and power only with less than 1% mean error. Owing to these benefits due to lower computational complexity, the multiplier can be configured to achieve significant savings with a high quality output and that suits well to the nature of the speech processing systems, hence the design works well for the epoch extraction system in speech.

@inproceedings{bib_Low__2020, AUTHOR = {Yadav, Battu Balaji and Mounika, Kelam and De, Koushik and Abbas, Zia }, TITLE = {Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2020}}

This brief presents a novel low-power and area-efficient LDO that satisfies all primary requirements of power mapping for a Power Management IC (PMIC). The design introduces a dynamically biased feedback resistor which responds instantly to the output voltage variations, thereby achieving better load transient behavior. Besides, the employed adaptive-biasing technique contributes in architectural transformation to attain stability over a wider range of load currents (0–100mA). It provides a regulated voltage of 1.87V from a supply ranging from 1.92V to 3.6V with a reported load and line regulation of 0.00136mV/mA and 0.078mV/V respectively. Moreover, the circuit potentially supports the load transients either from 0A to 100mA or 100mA to 0A with a rise and fall times of 10 μs. The achieved overshoot and undershoot values are 160mV and 154mV respectively. Hence, it demonstrates a substantial steady-state and transient performance with low-power thus making it suitable for battery-operated portable devices.

@inproceedings{bib_67pp_2020, AUTHOR = {Yadav, Battu Balaji and Mounika, Kelam and Adithya, B and Abbas, Zia }, TITLE = {67ppm/° C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2020}}

This work presents a highly accurate current reference of 66nA for ultra-low power applications. A very low figure-of-merit (FOM) of 1.3501ppm/°C 2 is achieved on consuming a minimal quiescent current of 199.37nA. To cancel out process variations, the current subtraction technique is employed and a β-multiplier is used to compensate for mobility (μ) and threshold voltage (V th ). In addition, curvature compensation technique backed by PTAT and CTAT current cancellation is adopted to attain a lower temperature coefficient (TC). Hence, an imperceptible variation of accuracy with temperature and supply variations across all process corners is attained. An adopted trimming scheme further minimizes the overall process spread to ±1.515% without compromising on accuracy. Accordingly, a TC of 67.04ppm/°C over a wide temperature range of −50° C to 100° C is obtained. Furthermore, 1.413%/V line sensitivity (LS) in the supply range of 1.38V to 3V is observed. Low power consumption of 275.13nW@1.38V facilitates its use in high-performance low power applications.

@inproceedings{bib_Robu_2019, AUTHOR = {GUPTA, PRATEEK and Mandadapu, Harshini Chowdary and Shirisha, Gourishetty and Abbas, Zia }, TITLE = {Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms}, BOOKTITLE = {International Symposium on Quality Electronic Design}. YEAR = {2019}}

In this paper, the optimal transistor sizing of the digital cells has been obtained using Simulated Annealing algorithm and an Artificial Bee Colony algorithm and their results have been compared with nominal results for various nanoscale CMOS digital circuits. The goal is to minimize the leakage power keeping the other performance parameters such as propagation delays and the area in the bound. The simulations are done using HSPICE tool for 45nm and below using Metal gate High k Predictive Technology Model cards. To make sure of the unaffected working of all cells in the automotive applications, the temperature range and supply voltage has been taken between −55oC to 125oC and 0.95V to 1.05V respectively. The Overall reduction in leakage power achieved in the logic cells is up to 70% without any penalty in the critical path delay.

@inproceedings{bib_A_Hi_2019, AUTHOR = {Jain, Arpan and ALI, HULUVALLAY MOHAMMED ASHFAKH and Kiran, Lade Sai and Abbas, Zia }, TITLE = {A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2019}}

In this paper, a highly stable all CMOS current reference against temperature and supply variation is proposed. Current reference of 5µA and 50nA has been designed for low power and ultra-low power applications respectively. The reference architecture is based on ratio between the PTAT voltage and the PTAT resistance. The process insensitive temperature compensation is accomplished by dividing TC of voltage with process insensitive TC of resistor. A high PSRR, process independent voltage reference is designed for PTAT voltage. N-poly on chip resistor is used for PTAT resistance. The proposed current reference is implemented in 0.18-µm TSMC technology. The architecture achieved PSRR of 74dB and line sensitivity of 0.05% works at supply voltage variation from 1.4V to 3.6V. The current reference of 5µA and 50nA attain temperature coefficient of 11.6 ppm/oC and 12.2 ppm/oC respectively for the temperature variation of -55oC to 125oC.

@inproceedings{bib_PVT__2019, AUTHOR = {GUPTA, PRATEEK and Shirisha, Gourishetty and Mandadapu, Harshini Chowdary and Abbas, Zia }, TITLE = {PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit Design}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems 2019}. YEAR = {2019}}

Enormous increase in process variations (due to progressive CMOS technology scaling) along-with the temperature and supply voltage variations are severely degrading the fabrication outcome of digital circuits i.e. circuits are not accomplishing the specification bounds of the required performances. Therefore, process and operating variations aware optimization has become a very essential task in VLSI design. Moreover, many specifications in a circuit have challenging trade-offs, hence demand effective optimization skills. With this vision, this paper presents optimization algorithm based robust transistor sizing for various nanoscale CMOS digital circuits. The objective is to minimize the static i.e. leakage power without degrading the operating frequency (i.e. keeping the propagation delays in bound) and area. The reported results are shown for 32nm CMOS Metal gate High-k model parameters, however methodology is equally valid for further scaled technology nodes. The Overall reduction in leakage power obtained is up to 88% keeping bound on the critical path delay. The temperature range and supply voltage has been taken between −55◦C to +125◦C (for automotive applications) and 0.90V to 1.10V (±10% variations) respectively at 3-sigma design.

@inproceedings{bib_Stat_2019, AUTHOR = {AMURU, DEEPTHI and Zahra, Andleeb and Abbas, Zia }, TITLE = {Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models}, BOOKTITLE = {International Symposium on VLSI Design and Test}. YEAR = {2019}}

With the technology scaling down to sub-50 nm regime, the necessity of process variation aware estimation of Leakage Power is emphasized for robust digital circuit design. Variations in Leakage power results in a large increase in the variation of total power dissipation. This paper presents a Regression based estimation of leakage powers and total power dissipation in nanoscale standard cell-based designs that show an impressive speed-up advantage with respect to analog SPICE-level simulation. We propose a statistical variation aware estimation model through a Multivariate Linear Regression (MLR) and Multivariate Polynomial Regression (MPR) techniques. Exhaustive tests report shows MPR technique outperforms MLR technique in estimating the leakage and total power for the targeted 16 nm CMOS technology with negligible error (<1%). The proposed methodology works as black box i.e. equally valid for 16 nm, 22 nm and 45 nm technology nodes.

@inproceedings{bib_A_47_2019, AUTHOR = {ALI, HULUVALLAY MOHAMMED ASHFAKH and Kiran, Lade Sai and Jain, Arpan and Abbas, Zia }, TITLE = {A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications}, BOOKTITLE = {IEEE Transactions on Very Large Scale Integration Systems}. YEAR = {2019}}

A sub 1−V , ultra low power temperature sensor has been implemented in TSMC 180 nm. The architecture is digital friendly since it creates a pulse width modulated wave instead of voltage. It uses proportional to absolute temperature(PTAT) characteristics of resistance to generate PTAT delay. Temperature to delay conversion depends only on passive elements, thereby making the circuit insensitive to supply variations. Line sensitivity of 0.23 ◦C/V is achieved for a wide supply range of 0.7−3.6 V . A non linearity error of less than 0.8 ◦C is measured for −55 to 125 ◦C using linear fit curve. This occupies an area of 0.82 mm2 and consumes a power of 47 nW at 0.8 V supply.

@inproceedings{bib_A_Hi_2019, AUTHOR = {Shirisha, Gourishetty and Mandadapu, Harshini Chowdary and Zahra, Andleeb and Abbas, Zia }, TITLE = {A Highly Accurate Machine Learning Approach to Modelling PVT Variation Aware Leakage Power in FinFET Digital Circuits}, BOOKTITLE = {Asia Pacific Conference on Circuits and Systems}. YEAR = {2019}}

Due to the advent of deep sub-micron technologies, statistical (in addition to temperature and supply voltage) variations aware estimation of leakages power has become prominent. Also, estimation of leakage currents at SPICE level guarantees the most accurate results, however not feasible means in high complexity ICs. This performs adversely for Monte-Carlo iterations for statistical analysis. In this paper we introduced an accurate machine learning technique to model statistical and operating variation aware estimation from Artificial Neural Network and regression based Multivariate Polynomial Regression which exhibits innately faster computation and attained error less than 1% for the targeted 16nm FinFET technology node although model is black box for any technology. The accuracy of the proposed technique has been tested over several basic cells and estimation of the complex circuits have been carried out utilizing the pre-modelled basic cells.

@inproceedings{bib_A_Me_2019, AUTHOR = {M, Salman Ahmed and Abbas, Zia }, TITLE = {A Memetic Algorithm Based PVT Variation-Aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design}, BOOKTITLE = {International Conference on Computer Design}. YEAR = {2019}}

Higher yield, climbing transistor counts and shrinking dimensions of a single Integrated Circuit (IC) have always been the demands in the fabrication market. However, this increased complexity and miniaturization of transistors present a challenge, due to high critical process variations combined with a ubiquitous presence of temperature and supply voltage variations, to achieve the required specification bounds on the desired performance of the circuits. Since optimization has become a very crucial task in IC design, the paper presents an efficient transistor sizing based optimization technique of the CMOS circuits to achieve low power, high performance and high yield design goals. The proposed memetic algorithm judiciously utilizes a threshold based local search procedure to improve convergence in its inherent genetic nature. The algorithm optimizes with the effect of temperature ሾെ૞૞ܗܜ૞૛૚ሿԨ and supply voltage േ૚૙Ψ variations and in addition a number of statistically sampled sets generated as Gaussian, Latin Hypercube and Correlation Screened schemes of process variations. The proposed technique is applicable to any technology node and has been tested over several standard single-stage and some complex multi-stage digital circuits designed using a Multi-Gate high-K dielectric (MGK) 22nm CMOS model. The reduction in leakage power with propagation delay goes as high as ૞૜Ψ with ૢΨ respectively, as observed across the various digital circuits

@inproceedings{bib_Opti_2019, AUTHOR = {Sai, Kalluru Hema and Abbas, Zia }, TITLE = {Optimal Power-Area Polar Decoder Design based on Iterative Decomposition Technique}, BOOKTITLE = {India Council International Conference}. YEAR = {2019}}

Polar codes have a very good error correcting capacity compared to turbo and LDPC codes of similar length. They are the first to attain the channel capacity. The aim of the proposed work is to design an Area and Power optimal 2b SC polar decoder exhibiting reduced area and power without degrading the latency by iterative decomposition technique. The targeted performances in decoder architecture are achieved by novel reformulation of F-node, G-node and P-nodes.

@inproceedings{bib_Geom_2018, AUTHOR = {Abbas, Zia and Zahra, Dr. Andleeb and Olivieri, Mauro and Mastrandrea, Antonio }, TITLE = {Geometry Scaling Impact on Leakage Currents in FinFET Standard Cells Based on a Logic-Level Leakage Estimation Technique}, BOOKTITLE = {Microelectronics, Electromagnetics and Telecommunications}. YEAR = {2018}}

Static power consumption is one of the most critical issues in CMOS digital circuits, and FinFET technology is being recognized as a valid solution for the problem. In this chapter, we utilize a logic-level leakage current estimation technique relying on an internal node voltage-based model. The model is implemented in the form of VHDL packages. By utilizing the capability of the model, the behavior of major leakage component has been analyzed separately for FinFET technology scaling over single- and multi-stage digital standard cells.

@inproceedings{bib_Mult_2018, AUTHOR = {GUPTA, PRATEEK and Abbas, Zia }, TITLE = {Multi-Objective Optimization Algorithm Based Transistor Sizing for Improved Power-Delay-Area in Digital Circuits}, BOOKTITLE = {India Council International Conference}. YEAR = {2018}}

The goal of this paper is to obtain the robust transistor sizing of the digital logic circuits by minimizing the leakage power keeping the other performance parameters such as propagation delays and area in the bound. To perform such action, Simulated Annealing based Multi-Objective Optimization algorithm has been implemented and further improved the reduction in leakage power using Gradient Descent (MO-SAGRAD).The algorithms are implemented in python and the performance parameters are computed using HSPICE tool at 45nm, 22nmtechnology nodes with Metal Gate High K PTM model cards. Toensure the unruffled functioning of the cells in the automotive applications, the temperature range has been taken between−55oCto125oCrespectively and the supply voltage range istaken as 0.95V to 1.05V for 45nm and 0.76V to 0.84V for22nm technology node. The Overall reduction in leakage power achieved in the logic cells is up to 58% without any penalty in the critical path delay.

@inproceedings{bib_LEAD_2018, AUTHOR = {Abbas, Zia and Zahra, Andleeb and Olivieri, Mauro }, TITLE = {LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16nm CMOS Circuits}, BOOKTITLE = {International Symposium on VLSI Design and Test}. YEAR = {2018}}

Fast-computable and accurate leakage models for state of the art CMOS digital standard cells is one of the most critical issues in present and future nano-scale technology nodes. It is further interesting if such model can calculate leakage currents not only at initial circuit life but also over the years based on Bias Temperature Instability (BTI) aging mechanism, which increases the threshold voltage over the years – thus mitigating leakage – but in turn degrades circuit speed. A reliable quantification of such aging-induced leakage mitigation opens the way to effective trade-off techniques for compensating speed degradation while maintaining leakage within specification bounds. The presented logic level leakage characterization and estimation technique, currently implemented as VHDL packages, shows more than 103 speed-ups over HSPICE circuit simulation and exhibits less than 1% error over HSPICE. We report BTI aging aware leakage current estimation for ten years at 25 °C and 90 °C in 16 nm CMOS technology, and we analyze how such leakage reduction trend can be traded off to improve the degraded circuit speed over time.

@inproceedings{bib_Volt_2018, AUTHOR = {ALI, HULUVALLAY MOHAMMED ASHFAKH and Jain, Arpan and Abbas, Zia }, TITLE = {Voltage Level Adapter Design for High Voltage Swing Applications in CMOS Differential Amplifier}, BOOKTITLE = {International Symposium on VLSI Design and Test}. YEAR = {2018}}

This work focuses on circuit level technique that achieves high swing in single ended output differential amplifiers like differential amplifier with active current mirror load, telescopic cascode, folded cascode etc. This technique is designed in such a manner that it can be visualized as a 2-terminal black box. Now, these 2-terminals can be connected to the conventional single ended differential amplifiers enhancing their swing without degrading other parameters like gain, bandwidth, CMRR etc. This black box achieves its performance consuming less power and minimum circuitry area. All the simulation characterization and validation has been made through UMC 180 nm technology node in Cadence.

@inproceedings{bib_Opti_2018, AUTHOR = {GUPTA, PRATEEK and KUMAR, SHUBHAM and Abbas, Zia }, TITLE = {Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power}, BOOKTITLE = {International Symposium on VLSI Design and Test}. YEAR = {2018}}

In this paper, two one-bit full adder design techniques are explored for reduced power consumption in standby mode. The proposed algorithm based techniques compute optimal transistor sizing for variable operating conditions (temperature, supply voltage) to achieve desirable leakage power and speed for a full-adder circuit. Both techniques use ‘SLEEP’ signal to drive full adder circuit to lower standby mode leakage state without even degrading the performances in active mode. The investigation has been carried out for 45 nm, 32 nm, 22 nm Metal Gate High-K PTM models and all the simulation characterizations are carried out using HSPICE simulation tool. Performance comparison of both techniques after optimization has been done over a complete range temperature (−40 ∘ C−125 ∘ C) and ±5% variation in supply voltage. The resultant designs are tested on large full-adder based digital circuits to analyze the reduced standby leakage power. The results show that up to 97% of standby leakage reduction can be obtained with (0.4–15)% delay overhead using the proposed methods of full-adder design.

@inproceedings{bib_Yiel_2016, AUTHOR = {Abbas, Zia and Olivier, Mauro and Ripp, Andreas }, TITLE = {Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations}, BOOKTITLE = {Journal of Computational Electronics}. YEAR = {2016}}

We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. The final design solutions present transistor sizing, which depart from intuitive transistor sizing criteria and show dramatic yield improvements, which have been verified by Monte Carlo SPICE analysis.

@inproceedings{bib_Vari_2015, AUTHOR = {Khalid, Usman and Mastrandrea, Antonio and Abbas, Zia and Olivieri, Mauro }, TITLE = {Variability Aware Modeling of SEU Induced Failure Probability of Logic Circuit Paths in Static Conditions}, BOOKTITLE = {International Conference on Reliability, Infocom Technologies and Optimization}. YEAR = {2015}}

Voltage noise can lead to various errors such as dynamic and permanent, which are directly associated to circuit-level reliability issues. Variability in process parameters directly affects the probability of failures associated to voltage noise. Yet, the evaluation of the probability of failures by SPICE level Monte Carlo simulation is prohibitively time-consuming. This work proposes a technique to characterize the input noise and process variations in order to estimate failure probability in a logic circuit path composed of combinational cells and registers. The method allows to correctly estimate the order of magnitude of the probability of failures and to evidence the influence of process variations, while reaching >104 speedup versus SPICE.

@inproceedings{bib_Opti_2015, AUTHOR = {Abbas, Zia and Olivier, Mauro and Khalid, Usman and Ripp, Andreas and Pronath, Michael }, TITLE = {Optimal nbti degradation and pvt variation resistant device sizing in a full adder cell}, BOOKTITLE = {International Conference on Reliability, Infocom Technologies and Optimization}. YEAR = {2015}}

Aging phenomena, on top of process variations along with temperature and supply voltage variations, translate into complex degradation effects on the required performance and yield of nanoscale circuits. The proposed paper focuses on the development of mathematically optimal circuit sizing for yield maximization on the case study of a CMOS full adder circuit. The final cell design is robust against NBTI aging effects, impact of statistical (global and mismatch) and operating variation of temperature and supply voltage. Monte Carlo analysis has been carried out to verify the estimated yields. The demonstrated technique can be extended to a library of optimally designed digital cells

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