@inproceedings{bib_Qual_2023, AUTHOR = {Prasha Srivastava, Pawan Kumar, Zia Abbas}, TITLE = {Qualitative Data Augmentation for Performance Prediction in VLSI Circuits}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2023}}
Various studies have shown the advantages of using Machine Learning (ML) techniques for analog and digital IC design automation and optimization. Data scarcity is still an issue for electronic designs, while training highly accurate ML models. This work proposes generating and evaluating artificial data using generative adversarial networks (GANs) for circuit data to aid and improve the accuracy of ML models trained with a small training data set. The training data is obtained by various simulations in the Cadence Virtuoso, HSPICE, and Microcap design environment with TSMC 180nm and 22nm CMOS technology nodes. The artificial data is generated and tested for an appropriate set of analog and digital circuits. The experimental results show that the proposed artificial data generation significantly improves ML models and reduces the percentage error by more than 50% of the original percentage error, which were previously trained with insufficient data. Furthermore, this research aims to contribute to the extensive application of AI/ML in the field of VLSI design and technology by relieving the training data availability-related challenges.
Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture
Mohammed Salman Ahmed,Md Kalesha,Dr. Andleeb Zahra,Zia Abbas
@inproceedings{bib_Appr_2023, AUTHOR = {Mohammed Salman Ahmed, Md Kalesha, Dr. Andleeb Zahra, Zia Abbas}, TITLE = {Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture}, BOOKTITLE = {Integration}. YEAR = {2023}}
Approximate Computing techniques are finding a central role in modern applications, by optimizing architectures to relax some computation but with a constrained inaccuracy. In many applications, the FFT algorithm is invariably applied and there is a need for approximate low energy hardware solutions to the FFT. The paper thus proposes an approximate, fixed-point, in-place, shared memory architecture for FFT. It is well observed that the energy at FFT I/Os is not strictly contiguous, hence the proposed FFT exploits this window to tune the error. The proposed FFT and its associated butterfly unit is constructed to efficiently incorporate approximate Toom–Cook multiplication. As said, a supporting function in error correction based on the sparsity patterns, is a feature of this design. The design synthesized at 32 n m shows on average, a 48.6% and 52.8% improvement in consumption of area and energy, respectively …
DEEPTHI AMURU,Harsha V. Vudumula,Cherupally Pavan Kalyan Reddy,Gurram Sushanth Reddy,Amir Ahmad,Dr. Andleeb Zahra,Zia Abbas
@inproceedings{bib_AI/M_2023, AUTHOR = {DEEPTHI AMURU, Harsha V. Vudumula, Cherupally Pavan Kalyan Reddy, Gurram Sushanth Reddy, Amir Ahmad, Dr. Andleeb Zahra, Zia Abbas}, TITLE = {AI/ML algorithms and applications in VLSI design and technology}, BOOKTITLE = {Integration}. YEAR = {2023}}
An evident challenge ahead for the integrated circuit (IC) industry is the investigation and development of methods to reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual, timeconsuming, and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-largescale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past toward VLSI design and manufacturing. Moreover, we discuss the future scope of AI/ML applications to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations.
Design and fabrication methods of runtime self-tuning analog integrated circuits using machine learning
@inproceedings{bib_Desi_2023, AUTHOR = {Koushik De, Khanh Minh Le, DEEPTHI AMURU, Zia Abbas}, TITLE = {Design and fabrication methods of runtime self-tuning analog integrated circuits using machine learning}, BOOKTITLE = {United States Patent}. YEAR = {2023}}
An Integrated Circuit with an automatically re-tuning analog circuit is provided. The Integrated Circuit comprises (a) an analog circuit comprising a plurality of tunable components each configured to respond to a plurality of change control bits, (b) a Process, Voltage Temperature (PVT) characteristics monitor comprising a plurality of PVT sensors, (c) a tuning memory embedded with a machine learning (ML) model of the analog circuit and (d) an artificial intelligence (AI) engine configured to receive a PVT signal input from the plurality of PVT sensors and the machine learning model embedded in the tuning memory. Each tunable component is configured to change its electrical characteristics such that together each of the tunable components is enabled to retune the analog circuit to attain a predefined set of electrical characteristics.
PROPORTIONAL TO ABSOLUTE TEMPERATURE (PTAT) VOLTAGE GENERATING CIRCUIT FOR GENERATING A PTAT VOLTAGE AND ACTS AS A TEMPERATURE SENSOR
@inproceedings{bib_PROP_2023, AUTHOR = {Zia Abbas, P V Abhishek, HULUVALLAY MOHAMMED ASHFAKH ALI, Arpan Jain}, TITLE = {PROPORTIONAL TO ABSOLUTE TEMPERATURE (PTAT) VOLTAGE GENERATING CIRCUIT FOR GENERATING A PTAT VOLTAGE AND ACTS AS A TEMPERATURE SENSOR}, BOOKTITLE = {United States Patent}. YEAR = {2023}}
A proportional to-absolute-temperature (PTAT) voltage generating circuit connected between a power supply voltage source and a ground for providing a PTAT voltage at an output terminal of the PTAT voltage generating circuit to act as a temperature sensor is provided. The PTAT voltage generating circuit includes a plurality of PMOS transistors. The plurality of PMOS transistors generates a second PTAT voltage by multiplying a first PTAT voltage by a factor equal to a ratio of a first equivalent resistance (R2) and a second resistance (R1) of a first PMOS transistor (M4). The first equivalent resistance (R2) is obtained from a series combination of the plurality of PMOS transistors. The first PTAT voltage is generated by determining a difference between a base-emitter voltage of a first PNP transistor (T1) and the second PNP transistor
Fast and efficient ResNN and Genetic optimization for PVT aware performance enhancement in digital circuits
@inproceedings{bib_Fast_2022, AUTHOR = {Kushagra Agarwal, Aryamaan Jain, Deepthi Amuru, Zia Abbas}, TITLE = {Fast and efficient ResNN and Genetic optimization for PVT aware performance enhancement in digital circuits}, BOOKTITLE = {International Symposium on VLSI Design, Automation and Test}. YEAR = {2022}}
This paper presents a fast and efficient optimization engine with multi-directional, multi-objective algorithms based on a robust transistor sizing approach to improve digital circuit performance. However, such optimization processes are highly simulator-dependent and computationally expensive tasks. Therefore, we propose developing machine learning-based reliable models considering process and operating variations to speed up the optimization procedure by running them on developed Residual Neural Network (ResNN) models instead of running expensive circuit simulations. Results on 22nm Metal Gate HighK digital cells show a reduction in delay and leakage up to 36.7% and 18.8%, respectively improving computational efficiency by several orders.
System and method for analog design synthesis using analog cell component library based on ai/ml
@inproceedings{bib_Syst_2022, AUTHOR = {Zia Abbas, Koushik De}, TITLE = {System and method for analog design synthesis using analog cell component library based on ai/ml}, BOOKTITLE = {United States Patent}. YEAR = {2022}}
A system and method for synthesizing analog design in real - time using an artificial intelligence and machine learn ing ( AI / ML ) model are provided . The method includes ( i ) generating a behavioral model of an analog macro using the AI / ML model ; ( ii ) determining one or more operations that is required to implement the behavioral model by scanning the behavioral model ; ( iii ) selecting , using the AI / ML model , the analog macro based on at least one specification that corresponds to the analog macro ; ( iv ) synthesizing , the analog macro that is selected by the AI / ML model 214 and one or more leaf cells for each selected analog macro of the behavioral architectural implementation to obtain a gate level circuit design based on a figure of merit ( FoM ) of the analog macro and ( v ) determining , using the AI / ML model , the analog circuit design for the integrated circuit system based on the gate level circuit design that is synthesized .
@inproceedings{bib_Impl_2022, AUTHOR = {Annapurna Kamadi, Zia Abbas}, TITLE = {Implementation of TRNG with SHA-3 for hardware security}, BOOKTITLE = {Microelectronic Journal}. YEAR = {2022}}
Random Number Generators (RNGs) are the solution for cryptographic applications to enhance hardware security. These RNGs ought to have three specific properties unpredictability, aperiodic, and good statistical criteria. This brief presents a True Random Number Generator (TRNG) based on Ring oscillators’ jitter with MLFSR. The MLFSR is augmented with a set of prime primitive polynomials, Boolean, and non-linear functions to attain a non-linear, unpredictable, and extended sequence period. Paper mainly focused on achieving high randomness by integrated the TRNG with a new promising crypto engine Keccak as a post-processing block; leads to extensively more security in data transfer, encryption keys, data authenticity of ICs, and IoT based applications. The RNG design is coded in Verilog HDL and implemented on the FPGA Zed board. Hashing is performed with a throughput of 2.4Gbps at 100 MHz either with RNG data or SHA data. Evaluated the randomness of the generated non-deterministic bitstreams (10 Mb) using the NIST 800–22 & Diehard test suite and successfully passed.
Deepthi Amuru,Harsha V Vudumula, Pavan K Cherupally, Sushanth R Gurram,Amir Ahmad,Andleeb Zahra,Zia Abbas
@inproceedings{bib_AI/M_2022, AUTHOR = {Deepthi Amuru, Harsha V Vudumula, Pavan K Cherupally, Sushanth R Gurram, Amir Ahmad, Andleeb Zahra, Zia Abbas}, TITLE = {AI/ML Algorithms and Applications in VLSI Design and Technology}, BOOKTITLE = {Technical Report}. YEAR = {2022}}
An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and dataintensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations.
A Novel Smart Belt for Anxiety Detection, Classification, and Reduction Using IIoMT on Students’ Cardiac Signal and MSY
Rishi Pal,Deepak Adhikari,Md Belal Bin Heyat,Md Belal Bin Heyat,Vivian Lipari,Julien Brito Ballester,Isabel De la Torre Díez,Zia Abbas,Dakun Lai ,Dakun Lai
@inproceedings{bib_A_No_2022, AUTHOR = {Rishi Pal, Deepak Adhikari, Md Belal Bin Heyat, Md Belal Bin Heyat, Vivian Lipari, Julien Brito Ballester, Isabel De La Torre Díez, Zia Abbas, Dakun Lai , Dakun Lai }, TITLE = {A Novel Smart Belt for Anxiety Detection, Classification, and Reduction Using IIoMT on Students’ Cardiac Signal and MSY}, BOOKTITLE = {Bioengineering}. YEAR = {2022}}
A Novel Smart Belt for Anxiety Detection, Classification, and Reduction Using IIoMT on Students’ Cardiac Signal and MSY
Thermal Study of Thin-Film Heater for PCR Reaction-Based Applications
Dr. Andleeb Zahra,Giampiero de Cesare,Domenico Caputo,Zia Abbas
Microactuators, Microsensors and Micromechanisms:, MAMM, 2022
Abs | | bib Tex
@inproceedings{bib_Ther_2022, AUTHOR = {Dr. Andleeb Zahra, Giampiero De Cesare, Domenico Caputo, Zia Abbas}, TITLE = {Thermal Study of Thin-Film Heater for PCR Reaction-Based Applications}, BOOKTITLE = {Microactuators, Microsensors and Micromechanisms:}. YEAR = {2022}}
This paper presents the design, fabrication, and characterization of a thin-film Cr-Al-Cr (300 A°-1500 A°-300 A°) metal stack heater specially designed for chemical reactions which occur at a uniform temperature in the lab on a chip platform such as polymerase chain reaction (PCR) applications. The heater has been designed using COMSOL Multiphysics. The simulated design has been fabricated using lithography and patterning on a 5 × 5 cm2 glass substrate. For the validation of the proposed design thermal study of the fabricated heater has also been done using a FLIR IR camera. A very good agreement between the thermal image of modeled and fabricated heater has been achieved. This demonstrates the suitability of the proposed heater for PCR reaction applications.
An End-to-End Cardiac Arrhythmia Recognition Method with an Effective DenseNet Model on Imbalanced Datasets Using ECG Signal
Hadaate Ullah,Md Belal Bin Heyat,Faijan Akhtar,Abdullah Y Muaad,Md Islam,Zia Abbas,Taisong Pan,Min Gao,Yuan Lin
Computational Intelligence and Neuroscience, CIN, 2022
Abs | | bib Tex
@inproceedings{bib_An_E_2022, AUTHOR = {Hadaate Ullah, Md Belal Bin Heyat, Faijan Akhtar, Abdullah Y Muaad, Md Islam, Zia Abbas, Taisong Pan, Min Gao, Yuan Lin}, TITLE = {An End-to-End Cardiac Arrhythmia Recognition Method with an Effective DenseNet Model on Imbalanced Datasets Using ECG Signal}, BOOKTITLE = {Computational Intelligence and Neuroscience}. YEAR = {2022}}
Electrocardiography (ECG) is a well-known noninvasive technique in medical science that provides information about the heart’s rhythm and current conditions. Automatic ECG arrhythmia diagnosis relieves doctors’ workload and improves diagnosis effectiveness and efficiency. This study proposes an automatic end-to-end 2D CNN (two-dimensional convolution neural networks) deep learning method with an effective DenseNet model for addressing arrhythmias recognition. To begin, the proposed model is trained and evaluated on the 97720 and 141404 beat images extracted from the Massachusetts Institute of Technology-Beth Israel Hospital (MIT-BIH) arrhythmia and St. Petersburg Institute of Cardiological Technics (INCART) datasets (both are imbalanced class datasets) using a stratified 5-fold evaluation strategy. The data is classified into four groups: N (normal), V (ventricular ectopic), S (supraventricular ectopic), and F (fusion), based on the Association for the Advancement of Medical Instrumentation® (AAMI). The experimental results show that the proposed model outperforms state-of-the-art models for recognizing arrhythmias, with the accuracy of 99.80% and 99.63%, precision of 98.34% and 98.94%, and F1-score of 98.91% and 98.91% on the MIT-BIH arrhythmia and INCART datasets, respectively. Using a transfer learning mechanism, the proposed model is also evaluated with only five individuals of supraventricular MIT-BIH arrhythmia and five individuals of European ST-T datasets (both of which are also class imbalanced) and achieved satisfactory results. So, the proposed model is more generalized and could be a prosperous …
AI-driven self adapting microelectronic circuits
Khanh M Le,Koushik De,DEEPTHI AMURU,Zia Abbas
United States Patent, Us patent, 2022
@inproceedings{bib_AI-d_2022, AUTHOR = {Khanh M Le, Koushik De, DEEPTHI AMURU, Zia Abbas}, TITLE = {AI-driven self adapting microelectronic circuits}, BOOKTITLE = {United States Patent}. YEAR = {2022}}
The present description relates to a method based on artifi cial intelligence to implement a wide range of microelec tronic circuits that can adapt by themselves to the usage conditions ( e.g. loading changes ) , manufacturing variances or defects ( e.g. process variations , device parameter mis matches , device model inaccuracies or changes , etc. ) , as well as environmental conditions ( e.g. voltage , temperature , interference ) in order to negate all or part of their effects on the circuit performance characteristics and achieve a very tight set of specifications over the wide range of conditions . Each microelectronic circuit is represented by a neural network model whose behavior is a function of the actual input signals , the usage and environmental conditions . An attached AI engine will infer from the model , the input signals , the usage conditions and the environmental condi tions and create the adaptive changes required to modify the microelectronic circuit's behavior to negate all or part of their effects on the circuit performance characteristics and to achieve a very tight set of specifications .
A 9.5nW, 0.55V Supply, CMOS Current Reference for Low Power Biomedical Applications
Samriddhi Agarwal,Ashutosh Pathy,Zia Abbas
IEEE Transactions on Circuits and Systems II: Express Briefs, TCS-II, 2022
@inproceedings{bib_A_9._2022, AUTHOR = {Samriddhi Agarwal, Ashutosh Pathy, Zia Abbas}, TITLE = {A 9.5nW, 0.55V Supply, CMOS Current Reference for Low Power Biomedical Applications}, BOOKTITLE = {IEEE Transactions on Circuits and Systems II: Express Briefs}. YEAR = {2022}}
This brief proposes an ultra-low-power current ref- erence in TSMC 180nm technology. Temperature compensation is achieved by taking the ratio of compensated voltage and an on-chip resistance. This design uses the concept of the back- gate effect of critical MOSFET to generate complementary to absolute temperature (CTAT) voltage. The circuit works from a supply voltage of 0.55V and is designed for a reference current of 5.6nA. Furthermore, a pseudo-differential amplifier (PD-AMP) helps realize low line regulation of 0.022%/V in the supply range of 0.55 to 1.9V. An average temperature coefficient (TC) of 256.07ppm/◦C is achieved for mismatch and process variations in Monte-Carlo simulations for 1000 samples over a tempera- ture range of −30◦C to 70◦C. The circuit consumes only 9.5nW of power (at room temperature and minimum supply voltage), making it suitable for ultra-low-power biomedical applications. Index Terms—Peaking current reference, biomedical, sub- threshold region, DIBL, PD-AMP.
A 156pW Gate-Leakage Based Voltage/Current Reference for Low-Power IoT Systems
P V Abhishek,HULUVALLAY MOHAMMED ASHFAKH ALI,Arpan Jain,Inhee Lee,Zia Abbas
IEEE International Symposium on Circuits and Systems, ISCAS, 2022
@inproceedings{bib_A_15_2022, AUTHOR = {P V Abhishek, HULUVALLAY MOHAMMED ASHFAKH ALI, Arpan Jain, Inhee Lee, Zia Abbas}, TITLE = {A 156pW Gate-Leakage Based Voltage/Current Reference for Low-Power IoT Systems}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2022}}
The paper presents a sub-nW gate-leakage based voltage and current reference in a single circuit whose reference values are scalable and doesn’t incorporate start-up circuits or resistors in the architecture. The power consumption of the proposed circuit increases by only 2.1x in the temperature range of -55°C to 100°C, unlike conventional voltage/current references where the power consumption increases exponentially w.r.t temperature. Implemented in 90nm technology, the proposed voltage reference (current reference) achieves post-trim typical accuracy of 22ppm/°C(58ppm/°C) and worst-case accuracy of 71ppm/°C(78ppm/°C). Excellent line sensitivities of 0.029%/V and 0.059%/V are observed for voltage and current reference respectively, in a supply range of 1V - 3V. Without any start-up circuit, the observed 99% settling times for voltage and current reference are 1.92ms and 2.526ms respectively. The area occupied by the total circuit is 0.0015mm 2 , while the power consumption is 156pW at typical corner, 27°C and 1V supply.
A 180o Phase Shift Biasing Technique for Realizing High PSRR in Low Power Temperature Sensors
Arpan Jain,P V Abhishek,HULUVALLAY MOHAMMED ASHFAKH ALI,Zia Abbas
International Conference on VLSI Design, VLSID, 2022
@inproceedings{bib_A_18_2022, AUTHOR = {Arpan Jain, P V Abhishek, HULUVALLAY MOHAMMED ASHFAKH ALI, Zia Abbas}, TITLE = {A 180o Phase Shift Biasing Technique for Realizing High PSRR in Low Power Temperature Sensors}, BOOKTITLE = {International Conference on VLSI Design}. YEAR = {2022}}
The paper presents a low-cost method (no extra LDO, Op-amp) to increase the PSRR of composite pair based temperature sensor. Composite pair is a commonly used circuit to generate a linear PTAT voltage for a wide temperature range. A 180° phase shift, voltage biasing technique is introduced at the gate of the NMOS transistor to obtain a supply independent bias current in composite pair. The proposed technique thus achieves a high supply noise rejection. The circuit as a whole does not require additional circuitry, therefore it saves power and area. A 6μW Temperature sensor with 1mV/°c slope is designed in TSMC 180nm technology and achieves PSRR of -80dB. Post-layout simulation results show that the temperature sensor achieves inaccuracy of ±0.1°C from −55°C to 125°C, PSRR of −80dB at 105Hz and -70dB at 200kHz at 1V power supply, and the line regulation of 0.016%/V in a supply voltage range of 1V to 2.5V. Monte-Carlo simulation result for the output PSRR shows −80.56dB as the mean-value with a maximum deviation of ±1.5dB.
Investigation of the Mechanical Reliability of a Velostat-based Flexible Pressure Sensor
Anis Fatema,Ivin Kuriakose,Deeksha Devendra,Zia Abbas
IEEE International Conference on Flexible and Printable Sensors and Systems, FLEPS, 2022
@inproceedings{bib_Inve_2022, AUTHOR = {Anis Fatema, Ivin Kuriakose, Deeksha Devendra, Zia Abbas}, TITLE = {Investigation of the Mechanical Reliability of a Velostat-based Flexible Pressure Sensor}, BOOKTITLE = {IEEE International Conference on Flexible and Printable Sensors and Systems}. YEAR = {2022}}
The technological advancements in healthcare mon- itoring devices, automation, consumer electronics, and soft robotics have resulted in extensive research in flexible pressure, force, and tactile sensors. Piezoresistive sensors are the most widely used flexible pressure sensors due to their low-cost fabrication, high flexibility and simple data-acquisition circuits. In this paper, we report the bending response of a velostat- based flexible pressure sensor by examining its reliability when subjected to repeated mechanical stress. The observed deviation in output voltage was 0.95% for 15 mm, 0.95% for 20 mm, 0.97% for 25 mm, and 2.2% for 30 mm bending radii, for 150 bending cycles, with respect to the flat position. We present a two-parameter (a, b) calibration for the pressure sensor with a fixed bias resistance in the readout circuit. This model can be used to further minimize the deviation due to bending cycles. The results obtained from the experimental research have shown a practical possibility of implementing velostat-based sensors for both static and dynamic flexible systems. Index Terms—Reliability; piezoresistive; pressure sensor; me- chanical stress; velostat
ON-CHIP COMPLEMENTARY METAL-OXIDESEMICONDUCTOR (CMOS) RESISTANCE AMPLIFIER
Arpan Jain,HULUVALLAY MOHAMMED ASHFAKH ALI,Zia Abbas
@inproceedings{bib_ON-C_2021, AUTHOR = {Arpan Jain, HULUVALLAY MOHAMMED ASHFAKH ALI, Zia Abbas}, TITLE = {ON-CHIP COMPLEMENTARY METAL-OXIDESEMICONDUCTOR (CMOS) RESISTANCE AMPLIFIER}, BOOKTITLE = {INDIAN PATENT}. YEAR = {2021}}
[0002] Resistors are the essential and common elements of any electronic circuits and extensively used in electronic equipment. They are frequently used in Integrated Circuits. The conventional on-chip resistance takes a large silicon area compared to metal oxide 15 semiconductor MOS transistor. In fabrication, the area is proportional to cost. If the silicon area is more, then the cost of the chip also increases. Therefore, large resistances are avoided to fabricate on the chip. For low power circuits, large resistances are often required but due to limited silicon area they are avoided. Hence the conventional resistor is replaced by a complementary metal-oxide-semiconductor CMOS circuit or a switched capacitor-based 20 resistor circuit to save area.
A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Microsystems
P V Abhishek,HULUVALLAY MOHAMMED ASHFAKH ALI,Arpan Jain,B Adithya,Zia Abbas
IEEE International Symposium on Circuits and Systems, ISCAS, 2021
@inproceedings{bib_A_41_2021, AUTHOR = {P V Abhishek, HULUVALLAY MOHAMMED ASHFAKH ALI, Arpan Jain, B Adithya, Zia Abbas}, TITLE = {A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Microsystems}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2021}}
The paper presents a sub-nW BJT based temperature sensor for ultra-low power microsystems. The sensor is based on amplifying the difference between baseemitter voltages of BJTs using gate-leakage transistors. Implemented in UMC 65nm technology, the sensor occupies an area of 0.005mm2 . It achieves a maximum non-linearity error of 0.12oC(3σ) over the temperature range of −55oC to 80oC. Without any trimming, a worst case inaccuracy of +0.36oC/ − 1.61oC is observed w.r.t process variations, depicting the process-invariant nature of the temperature sensor. It also achieves a low supply sensitivity of 0.56oC/V over a wide supply range of 0.7V-3V. The power consumption of the sensor is 419pW at 27oC and 0.7V supply.
Algorithm driven Power-Timing Optimization Methodology for CMOS Digital Circuits considering PVTA Variations
Kalluru Hema Sai,Prasenjit Saha,Andleeb Zahra,Zia Abbas
IEEE International Symposium on Circuits and Systems, ISCAS, 2021
@inproceedings{bib_Algo_2021, AUTHOR = {Kalluru Hema Sai, Prasenjit Saha, Andleeb Zahra, Zia Abbas}, TITLE = {Algorithm driven Power-Timing Optimization Methodology for CMOS Digital Circuits considering PVTA Variations}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2021}}
In this paper, we aim at optimizing the leakage power and propagation delays using optimization algorithms like Glowworm Swarm Optimization and Neighbourhood Cultivation Genetic Algorithm, subjected to variations in Process, Voltage, Temperature and Aging degradation (PVTA) targeting low power or high performance applications. For high performance applications, we synthesize transistor sizes, at which the critical path delay in worst case PVT conditions with 3 years of NBTI aging degradation is optimized below the critical path delay (of initial sizing) at nominal conditions keeping power budget in bound. On the other hand, for low power applications, we obtain transistor sizing where leakage is reduced by more than 50%, keeping a bound on critical path delay. All the pre and post stress simulations are performed using HSPICE for 22nm Metal Gate High-K dielectric model parameters. The temperature range and the supply voltage ranges are −55 °C to 125 °C and 0.72V to 0.88V respectively. The process parameters are considered at ±3σ variation. The ingenuous working of the circuits for the obtained sizing is ensured by Monte Carlo analysis evaluating over entire range of process variations and operating conditions for intended life time.
Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells using Swarm Intelligence
Prasenjit Saha,Salman Ahmed M,Kalluru Hema Sai,Zia Abbas
IEEE International Symposium on Circuits and Systems, ISCAS, 2021
@inproceedings{bib_Low__2021, AUTHOR = {Prasenjit Saha, Salman Ahmed M, Kalluru Hema Sai, Zia Abbas}, TITLE = {Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells using Swarm Intelligence}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2021}}
This paper proposes low power optimization using a modified swarm intelligence algorithm for the scenariostransistor sizing based static power reduction and low power standard cell generation for approximate computing. In these scenarios, we explore a lower abstraction level and see how standard cells can be tuned to a power-delay-quality optimal point. For transistor sizing, the algorithm considers fabrication process parameter variations (for ±3σ design) in addition to a wide range of temperature (-55oC to 125oC) and supply voltage (±10%) variations to yield PVT aware robust sizing solutions. The approach has been applied on numerous single and multistage circuits (including ISCAS benchmarks) while proposing a dual sizing solution for non-critical and critical path cells. For approximate systems, we present algorithm-generated full adder designs for speech processing systems. The designs vary in terms of accuracy and power. Results show leakage reductions up to 58.2% for conventional and 66.8% with approximation designs for 22nm metal gate high-K (MGK) technology cells.
A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Micro systems
P V Abhishek,HULUVALLAY MOHAMMED ASHFAKH ALI,Arpan Jain,Adithya Banthi,Zia Abbas
IEEE International Symposium on Circuits and Systems , ISCAS, 2021
@inproceedings{bib_A_41_2021, AUTHOR = {P V Abhishek, HULUVALLAY MOHAMMED ASHFAKH ALI, Arpan Jain, Adithya Banthi, Zia Abbas}, TITLE = {A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Micro systems}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems }. YEAR = {2021}}
The paper presents a sub-nW BJT based temperature sensor for ultra-low power microsystems. The sensor is based on amplifying the difference between base-emitter voltages of BJTs using gate-leakage transistors. Implemented in UMC 65nm technology, the sensor occupies an area of 0.005mm 2 . It achieves a maximum non-linearity error of 0.12°C(3σ) over the temperature range of –55°C to 80°C. Without any trimming, a worst case inaccuracy of +0.36°C/ –1.61°C is observed w.r.t process variations, depicting the process-invariant nature of the temperature sensor. It also achieves a low supply sensitivity of 0.56°C/V over a wide supply range of 0.7V-3V. The power consumption of the sensor is 419pW at 27°C and 0.7V supply.
PVT and Aging Degradation Invariant Automated Optimization Approach for CMOS Low-Power High-Performance VLSI Circuits
Kalluru Hema Sai,Prasenjit Saha,Dr. Andleeb Zahra,Zia Abbas
International Symposium on Quality Electronic Design, ISQED, 2021
@inproceedings{bib_PVT__2021, AUTHOR = {Kalluru Hema Sai, Prasenjit Saha, Dr. Andleeb Zahra, Zia Abbas}, TITLE = {PVT and Aging Degradation Invariant Automated Optimization Approach for CMOS Low-Power High-Performance VLSI Circuits}, BOOKTITLE = {International Symposium on Quality Electronic Design}. YEAR = {2021}}
In this paper, we aim at optimizing the leakage power and propagation delays using optimization algorithms like Glowworm Swarm Optimization and Neighbourhood Cultivation Genetic Algorithm, subjected to variations in Process, Voltage, Temperature and Aging degradation (PVTA) targeting low power or high performance applications. For high performance applications, we synthesize transistor sizes, at which the critical path delay in worst case PVT conditions with 3 years of NBTI aging degradation is optimized below the critical path delay (of initial sizing) at nominal conditions keeping power budget in bound. On the other hand, for low power applications, we obtain transistor sizing where leakage is reduced by more than 50%, keeping a bound on critical path delay. We have also proposed a step by step optimization method for optimizing complex cells. All the pre and post stress simulations are performed using HSPICE for 22nm Metal Gate High-K dielectric model parameters. The temperature range and the supply voltage ranges are -55 °C to 125 °C and 0.72V to 0.88V respectively. The process parameters are considered at ±3σ variation. The ingenuous working of the circuits for the obtained sizing is ensured by Monte Carlo analysis evaluating over entire range of process variations and operating conditions for the intended life time.
Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence
Prasenjit Saha,Kalluru Hema Sai,Zia Abbas
International Conference on VLSI Design, VLSID, 2021
@inproceedings{bib_Tran_2021, AUTHOR = {Prasenjit Saha, Kalluru Hema Sai, Zia Abbas}, TITLE = {Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence}, BOOKTITLE = {International Conference on VLSI Design}. YEAR = {2021}}
This paper deals with transistor sizing based static power optimization for multi-stage CMOS circuits using swarm intelligence algorithm. The overall circuit performance is improved by optimizing the individual basic cell performances. Optimized cells are re-used at places with similar circuit scenarios thereby reducing the number of variables to work with. At each stage of execution, the algorithm generates multiple sizing options for basic cells with varying power-delay specifications to choose from. This work proposes a dual sizing approach for critical and non-critical path cells. The overall process has low circuit dependence and has been applied on a wide range of single and multi-stage circuits (including ISCAS benchmark circuits). The approach considers fabrication process parameter variations (for ±3σ design) in addition to a wide range of temperature (-55oC to 125oC) and supply voltage (±10%) variations for robust sizing solutions. Results show leakage reductions up to 63.6%.
A 443pW Accumulation-Mode Gate-Leakage Based Bandgap Reference for IoT Applications
Abhishek Pullela,HULUVALLAY MOHAMMED ASHFAKH ALI,Gurram Sushanth Reddy,Arpan Jain,Zia Abbas
International Midwest Symposium on Circuits and Systems, MWSCAS, 2021
@inproceedings{bib_A_44_2021, AUTHOR = {Abhishek Pullela, HULUVALLAY MOHAMMED ASHFAKH ALI, Gurram Sushanth Reddy, Arpan Jain, Zia Abbas}, TITLE = {A 443pW Accumulation-Mode Gate-Leakage Based Bandgap Reference for IoT Applications}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2021}}
—The paper presents a sub-nW bandgap reference (BGR) that exploits the temperature variation of gate-leakage current in thin oxide devices operating in the accumulation region to generate the reference voltage. The incorporation of gateleakage transistors scales down the power consumption of the BGR to pico-watt level without using any large physical resistors or sophisticated techniques, thereby making it suitable for IoT applications. The BGR is designed in TSMC 65nm technology and occupies an area of 0.009mm2 . Post layout simulation results show nominal and worst-case accuracies of 23ppm/oC and 44ppm/oC respectively in the temperature range of −40oC to 100oC. Without any trimming, an inaccuracy (±3σ) of 3% is observed for the reference voltage, showing its resilience to process variations. It also exhibits a typical line sensitivity of 0.063%/V in a supply range of 1.5V-3.8V and a PSRR of -65dB at DC and 1.8V supply. The power consumption is observed to be 443pW at 1.5V supply and nominal temperature.
AI-driven self adapting microelectronic circuits
Khanh M Le,Koushik De,Deepthi Amuru,Zia Abbas
United States Patent, Us patent, 2021
@inproceedings{bib_AI-d_2021, AUTHOR = {Khanh M Le, Koushik De, Deepthi Amuru, Zia Abbas}, TITLE = {AI-driven self adapting microelectronic circuits}, BOOKTITLE = {United States Patent}. YEAR = {2021}}
The present description relates to a method based on artifi cial intelligence to implement a wide range of microelec tronic circuits that can adapt by themselves to the usage conditions ( e.g. loading changes ) , manufacturing variances or defects ( e.g. process variations , device parameter mis matches , device model inaccuracies or changes , etc. ) , as well as environmental conditions ( e.g. voltage , temperature , interference ) in order to negate all or part of their effects on the circuit performance characteristics and achieve a very tight set of specifications over the wide range of conditions . Each microelectronic circuit is represented by a neural network model whose behavior is a function of the actual input signals , the usage and environmental conditions . An attached AI engine will infer from the model , the input signals , the usage conditions and the environmental condi tions and create the adaptive changes required to modify the microelectronic circuit's behavior to negate all or part of their effects on the circuit performance characteristics and to achieve a very tight set of specifications
A 0.85 V Supply, High PSRR CMOS Voltage Reference without Resistor and Amplifier for Ultra-Low Power Applications
Ashutosh Pathy,Banthi Adithya,Zia Abbas
International Midwest Symposium on Circuits and Systems, MWSCAS, 2021
@inproceedings{bib_A_0._2021, AUTHOR = {Ashutosh Pathy, Banthi Adithya, Zia Abbas}, TITLE = {A 0.85 V Supply, High PSRR CMOS Voltage Reference without Resistor and Amplifier for Ultra-Low Power Applications}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2021}}
This paper presents an ultra-low power CMOS voltage reference (CVR) which is free of amplifier and resistor. A current generator circuit is used to generate a supply independent current to bias the active load in the temperature compensation circuit. Drain-source voltage of two critical MOSFETs is made equal in the current generator circuit by using a feedback arrangement to ensure a high PSRR of -75dB for the reference voltage. Temperature compensation is achieved by using the complementary to absolute temperature (CTAT) nature of gatesource of a MOSFET operating in the subthreshold region and proportional to absolute temperature (PTAT) nature of conventional composite pair architecture. The proposed CVR is designed in TSMC 180nm technology. The circuit works desirably for a supply range of 0.85V to 2.3V while generating a reference voltage of around 0.68V. Maximum temperature coefficient (TC) of 184 ppm/˚C and minimum TC of 69 ppm/˚C are noted for mismatch and process variations in the Monte-Carlo simulation for 1000 samples. The circuit consumes only 46nW of power, which makes it suitable for ultra-low power applications.
A 0.85V Supply, High PSRR CMOS Voltage Reference without Resistor and Amplifier for UltraLow Power Applications
Ashutosh Pathy,Banthi Adithya,Zia Abbas
International Midwest Symposium on Circuits and Systems, MWSCAS, 2021
@inproceedings{bib_A_0._2021, AUTHOR = {Ashutosh Pathy, Banthi Adithya, Zia Abbas}, TITLE = {A 0.85V Supply, High PSRR CMOS Voltage Reference without Resistor and Amplifier for UltraLow Power Applications}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2021}}
This paper presents an ultra-low power CMOS voltage reference (CVR) which is free of amplifier and resistor. A current generator circuit is used to generate a supply independent current to bias the active load in the temperature compensation circuit. Drain-source voltage of two critical MOSFETs is made equal in the current generator circuit by using a feedback arrangement to ensure a high PSRR of -75dB for the reference voltage. Temperature compensation is achieved by using the complementary to absolute temperature (CTAT) nature of gatesource of a MOSFET operating in the subthreshold region and proportional to absolute temperature (PTAT) nature of conventional composite pair architecture. The proposed CVR is designed in TSMC 180nm technology. The circuit works desirably for a supply range of 0.85V to 2.3V while generating a reference voltage of around 0.68V. Maximum temperature coefficient (TC) of 184 ppm/˚C and minimum TC of 69 ppm/˚C are noted for mismatch and process variations in the Monte-Carlo simulation for 1000 samples. The circuit consumes only 46nW of power, which makes it suitable for ultra-low power applications. Keywords— CMOS voltage reference, Line sensitivity, Subthreshold region, Temperature compensation.
67ppm/° C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications
Battu Balaji Yadav,Kelam Mounika,B Adithya,Zia Abbas
IEEE International Symposium on Circuits and Systems, ISCAS, 2020
@inproceedings{bib_67pp_2020, AUTHOR = {Battu Balaji Yadav, Kelam Mounika, B Adithya, Zia Abbas}, TITLE = {67ppm/° C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2020}}
This work presents a highly accurate current reference of 66nA for ultra-low power applications. A very low figure-of-merit (FOM) of 1.3501ppm/°C 2 is achieved on consuming a minimal quiescent current of 199.37nA. To cancel out process variations, the current subtraction technique is employed and a β-multiplier is used to compensate for mobility (μ) and threshold voltage (V th ). In addition, curvature compensation technique backed by PTAT and CTAT current cancellation is adopted to attain a lower temperature coefficient (TC). Hence, an imperceptible variation of accuracy with temperature and supply variations across all process corners is attained. An adopted trimming scheme further minimizes the overall process spread to ±1.515% without compromising on accuracy. Accordingly, a TC of 67.04ppm/°C over a wide temperature range of −50° C to 100° C is obtained. Furthermore, 1.413%/V line sensitivity (LS) in the supply range of 1.38V to 3V is observed. Low power consumption of 275.13nW@1.38V facilitates its use in high-performance low power applications.
Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance
Battu Balaji Yadav,Kelam Mounika,Koushik De,Zia Abbas
IEEE International Symposium on Circuits and Systems, ISCAS, 2020
@inproceedings{bib_Low__2020, AUTHOR = {Battu Balaji Yadav, Kelam Mounika, Koushik De, Zia Abbas}, TITLE = {Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2020}}
This brief presents a novel low-power and area-efficient LDO that satisfies all primary requirements of power mapping for a Power Management IC (PMIC). The design introduces a dynamically biased feedback resistor which responds instantly to the output voltage variations, thereby achieving better load transient behavior. Besides, the employed adaptive-biasing technique contributes in architectural transformation to attain stability over a wider range of load currents (0–100mA). It provides a regulated voltage of 1.87V from a supply ranging from 1.92V to 3.6V with a reported load and line regulation of 0.00136mV/mA and 0.078mV/V respectively. Moreover, the circuit potentially supports the load transients either from 0A to 100mA or 100mA to 0A with a rise and fall times of 10 μs. The achieved overshoot and undershoot values are 160mV and 154mV respectively. Hence, it demonstrates a substantial steady-state and transient performance with low-power thus making it suitable for battery-operated portable devices.
ATM: Approximate Toom-Cook Multiplication for Speech Processing Applications
Salman Ahmed M,DEEPTHI AMURU,Zia Abbas
IEEE International Symposium on Circuits and Systems, ISCAS, 2020
@inproceedings{bib_ATM:_2020, AUTHOR = {Salman Ahmed M, DEEPTHI AMURU, Zia Abbas}, TITLE = {ATM: Approximate Toom-Cook Multiplication for Speech Processing Applications}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2020}}
Approximate Computing has paved way for elaborate savings in design area and latency of modern system architectures processing images or signals, by a deliberate yet tolerable loss of functional accuracy. This paper thus proposes a design of an approximate multiplier based on the efficient Toom-Cook algorithm, that has a lower complexity of O(N logd(zd−1) ) than O(N 2 ), for order d. Inherent integer divisions in the algorithm has restricted its feasibility in hardware, unless without suitable approximation. On an average, the proposed multiplier achieves 53%, 18% and 57% improvements in area, delay and power only with less than 1% mean error. Owing to these benefits due to lower computational complexity, the multiplier can be configured to achieve significant savings with a high quality output and that suits well to the nature of the speech processing systems, hence the design works well for the epoch extraction system in speech.
An Efficient Gradient Boosting Approach for PVT Aware Estimation of Leakage Power and Propagation Delay in CMOS/FinFET Digital Cells
DEEPTHI AMURU,Salman Ahmed M,Zia Abbas
IEEE International Symposium on Circuits and Systems, ISCAS, 2020
@inproceedings{bib_An_E_2020, AUTHOR = {DEEPTHI AMURU, Salman Ahmed M, Zia Abbas}, TITLE = {An Efficient Gradient Boosting Approach for PVT Aware Estimation of Leakage Power and Propagation Delay in CMOS/FinFET Digital Cells}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2020}}
In this paper, we propose an accurate and computationally efficient Gradient Boosting approach for the estimation of statistical variations aware leakage power and propagation delay in the CMOS/FinFET standard digital cells. The proposed model estimates the leakage power and propagation delay w.r.t variations in process, temperature (−55°C to 125°C) and supply voltage(±10% variations). The distinguishing feature of the proposed approach is its compatibility with both CMOS and FinFET technologies. Moreover, the performance of the proposed model is consistent with various technology nodes. Exhaustive tests report an average error of <1% in 16nm CMOS and FinFET standard digital cells w.r.t analog HSPICE simulations with several orders increase in computational speed. Further, the complex cell estimation can be carried out through precharacterized standard cells abstaining longer simulations.
A Sub-nW, 8T Current Reference Consuming Constant Power wrt Process & Temperature
HULUVALLAY MOHAMMED ASHFAKH ALI,P V Abhishek,Arpan Jain,Zia Abbas
International Midwest Symposium on Circuits and Systems, MWSCAS, 2020
@inproceedings{bib_A_Su_2020, AUTHOR = {HULUVALLAY MOHAMMED ASHFAKH ALI, P V Abhishek, Arpan Jain, Zia Abbas}, TITLE = {A Sub-nW, 8T Current Reference Consuming Constant Power wrt Process & Temperature}, BOOKTITLE = {International Midwest Symposium on Circuits and Systems}. YEAR = {2020}}
he paper presents an eight transistor (8T) pico-watt current reference with a novel method of rectifying the prob-lem of exponential power increase w.r.t temperature in traditionalsub-nW references. The proposed current reference is obtainedby modifying the traditional beta-multiplier architecture to scale-down the power consumption without sacrificing area. Theconstancy of power consumption w.r.t temperature is achievedby exploiting the voltage-current characteristics of a leakagetransistor in the modified architecture. The proposed currentreference, implemented in UMC 55nm technology, occupies anarea of0.00035mm2. It is designed for a current of 60pA andachieves an accuracy of19ppm/0Cover a wide temperaturerange of−550Cto1250C. The reported line sensitivity for thecurrent reference is 0.07%/V in the supply range of 1.2V - 4V.Post-trim results show a constant power consumption of 144pWw.r.t temperature and process variations @1.2V supply.
A Compact, Power Efficient, Self-Adaptive and PVT Invariant CMOS Relaxation Oscillator
Kelam Mounika,Battu Balaji Yadav,Zia Abbas
Computer Society Annual Symposium on VLSI, ISVLSI, 2020
@inproceedings{bib_A_Co_2020, AUTHOR = {Kelam Mounika, Battu Balaji Yadav, Zia Abbas}, TITLE = {A Compact, Power Efficient, Self-Adaptive and PVT Invariant CMOS Relaxation Oscillator}, BOOKTITLE = {Computer Society Annual Symposium on VLSI}. YEAR = {2020}}
This brief presents a novel PVT-invariant CMOS relaxation oscillator for Real-Time Clock (RTC) applications. The proposed design is compatible to work in a low supply voltage domain of SoC. The PVT invariance is achieved by a unique circuit implementation of introducing a self-adaptive mechanism that dynamically modifies the time constant of the oscillator core. Moreover, the design is accompanied by a digital calibration unit for further process compensation. Besides, the introduced supply independent bias circuit has greatly improved the supply regulation of the oscillator frequency. In addition, the design utilizes a complementary to absolute temperature (CTAT) current for temperature compensation. Area efficiency is enhanced by replacing bigger passive device i.e, resistor with an adaptive MOS resistor. The obtained results show that the minimum temperature coefficient (TC) of 31.236ppm/°C is achieved over a range of -40°C to 100°C. The resultant phase noise of -140dBc/Hz@1MHz is observed. The design has achieved a good power efficiency of 1.65nW/KHz at room temperature without a calibration unit. The line sensitivity (LS) of 0.1159%/V is noted in the range of 0.7V to 1.2V. Nevertheless, the entire system occupies an active area of 0.0509mm^2 with a power consumption of 90nW@0.7V. Also, the leakage current of the complete system is <; 54pA. Therefore, the proposed design aims at providing a production-friendly, ease of integration and low-cost solution.
3.75ppm/°C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical Applications
Kelam Mounika,Battu Balaji Yadav,Zia Abbas
International Conference on VLSI Design, VLSID, 2020
@inproceedings{bib_3.75_2020, AUTHOR = {Kelam Mounika, Battu Balaji Yadav, Zia Abbas}, TITLE = {3.75ppm/°C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical Applications}, BOOKTITLE = {International Conference on VLSI Design}. YEAR = {2020}}
This brief presents a CMOS-only ultra low power voltage reference of 0.925V which is designed and simulated in TSMC 180nm technology. Current mixing between SelfBiased Self Cascode MOSFET (SBSCM) and Self Cascode MOSFET (SCM) pair is introduced along with stacking of proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltage generators to get second order curvature compensation. Temperature coefficient (TC) of 3.75ppm/°C over a wide temperature range of -55°C to 140°C is achieved. To feed on the power reduction requirement of low power biomedical applications, the entire circuit is designed in sub-threshold region. Therefore, the total power consumption is 27nW @ 1.45V at room temperature (27°C). Furthermore, a supply independent current bias aids in realizing high PSRR of -91dB @ 10Hz / -50dB @ 100MHz and line regulation of 0.0779%/V over a supply range 1.45V to 3.6V. Besides, an employed trimming technique attenuates the process spread from ±3% to ±0.3%. Moreover, the proposed design occupies an active area of 0.0054mm 2 only.
3.75ppm/◦C, -91dB PSRR, 27nW, 0.9V PVT Invarian Voltage Reference for Implantable Biomedical Applications
Battu Balaji Yadav,Zia Abbas
International Conference on VLSI Design, VLSID, 2020
@inproceedings{bib_3.75_2020, AUTHOR = {Battu Balaji Yadav, Zia Abbas}, TITLE = {3.75ppm/◦C, -91dB PSRR, 27nW, 0.9V PVT Invarian Voltage Reference for Implantable Biomedical Applications}, BOOKTITLE = {International Conference on VLSI Design}. YEAR = {2020}}
This brief presents a CMOS-only ultra low power voltage reference of 0.925V which is designed and simulated in TSMC 180nm technology. Current mixing between SelfBiased Self Cascode MOSFET (SBSCM) and Self Cascode MOSFET (SCM) pair is introduced along with stacking of proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltage generators to get second order curvature compensation. Temperature coefficient (TC) of 3.75ppm/◦C over a wide temperature range of -55◦C to 140◦C is achieved. To feed on the power reduction requirement of low power biomedical applications, the entire circuit is designed in sub-threshold region. Therefore, the total power consumption is 27nW @ 1.45V at room temperature (27◦C). Furthermore, a supply independent current bias aids in realizing high PSRR of -91dB @ 10Hz / -50dB @ 100MHz and line regulation of 0.0779%/V over a supply range 1.45V to 3.6V. Besides, an employed trimming technique attenuates the process spread from ±3% to ±0.3%. Moreover, the proposed design occupies an active area of 0.0054mm2 only. Index Terms—Ultra Low Power, Voltage Reference, PSRR, CTAT, PTAT, Biomedical, SBSCM, SCM.
67ppm/◦C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications
Battu Balaji Yadav,Kelam Mounika,Adithya Bathi,Zia Abbas
IEEE International Symposium on Circuits and Systems , ISCAS, 2020
@inproceedings{bib_67pp_2020, AUTHOR = {Battu Balaji Yadav, Kelam Mounika, Adithya Bathi, Zia Abbas}, TITLE = {67ppm/◦C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems }. YEAR = {2020}}
This work presents a highly accurate current reference of 66nA for ultra-low power applications. A very low figureof-merit (FOM) of 1.3501ppm/◦C 2 is achieved on consuming a minimal quiescent current of 199.37nA. To cancel out process variations, the current subtraction technique is employed and a β-multiplier is used to compensate for mobility (µ) and threshold voltage (Vth). In addition, curvature compensation technique backed by PTAT and CTAT current cancellation is adopted to attain a lower temperature coefficient (TC). Hence, an imperceptible variation of accuracy with temperature and supply variations across all process corners is attained. An adopted trimming scheme further minimizes the overall process spread to ±1.515% without compromising on accuracy. Accordingly, a TC of 67.04ppm/◦C over a wide temperature range of -50◦C to 100◦C is obtained. Furthermore, 1.413%/V line sensitivity (LS) in the supply range of 1.38V to 3V is observed. Low power consumption of 275.13nW@1.38V facilitates its use in high-performance low power applications. Index Terms—FOM, curvature compensation, Line Sensitivity, Proportional to Absolute Temperature (PTAT), Complementary to Absolute Temperature (CTAT), ZTC
Optimal Power-Area Polar Decoder Design based on Iterative Decomposition Technique
Kalluru Hema Sai,Zia Abbas
India Council International Conference, INDICON, 2019
@inproceedings{bib_Opti_2019, AUTHOR = {Kalluru Hema Sai, Zia Abbas}, TITLE = {Optimal Power-Area Polar Decoder Design based on Iterative Decomposition Technique}, BOOKTITLE = {India Council International Conference}. YEAR = {2019}}
Polar codes have a very good error correcting capacity compared to turbo and LDPC codes of similar length. They are the first to attain the channel capacity. The aim of the proposed work is to design an Area and Power optimal 2b SC polar decoder exhibiting reduced area and power without degrading the latency by iterative decomposition technique. The targeted performances in decoder architecture are achieved by novel reformulation of F-node, G-node and P-nodes.
A Memetic Algorithm Based PVT Variation-Aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design
Salman Ahmed M,Zia Abbas
International Conference on Computer Design, ICCD, 2019
@inproceedings{bib_A_Me_2019, AUTHOR = {Salman Ahmed M, Zia Abbas}, TITLE = {A Memetic Algorithm Based PVT Variation-Aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design}, BOOKTITLE = {International Conference on Computer Design}. YEAR = {2019}}
Higher yield, climbing transistor counts and shrinking dimensions of a single Integrated Circuit (IC) have always been the demands in the fabrication market. However, this increased complexity and miniaturization of transistors present a challenge, due to high critical process variations combined with a ubiquitous presence of temperature and supply voltage variations, to achieve the required specification bounds on the desired performance of the circuits. Since optimization has become a very crucial task in IC design, the paper presents an efficient transistor sizing based optimization technique of the CMOS circuits to achieve low power, high performance and high yield design goals. The proposed memetic algorithm judiciously utilizes a threshold based local search procedure to improve convergence in its inherent genetic nature. The algorithm optimizes with the effect of temperature ሾെܗܜሿԨ and supply voltage േΨ variations and in addition a number of statistically sampled sets generated as Gaussian, Latin Hypercube and Correlation Screened schemes of process variations. The proposed technique is applicable to any technology node and has been tested over several standard single-stage and some complex multi-stage digital circuits designed using a Multi-Gate high-K dielectric (MGK) 22nm CMOS model. The reduction in leakage power with propagation delay goes as high as Ψ with ૢΨ respectively, as observed across the various digital circuits
A Highly Accurate Machine Learning Approach to Modelling PVT Variation Aware Leakage Power in FinFET Digital Circuits
Gourishetty Shirisha,Harshini Chowdary Mandadapu,Andleeb Zahra,Zia Abbas
Asia Pacific Conference on Circuits and Systems, APCCAS, 2019
@inproceedings{bib_A_Hi_2019, AUTHOR = {Gourishetty Shirisha, Harshini Chowdary Mandadapu, Andleeb Zahra, Zia Abbas}, TITLE = {A Highly Accurate Machine Learning Approach to Modelling PVT Variation Aware Leakage Power in FinFET Digital Circuits}, BOOKTITLE = {Asia Pacific Conference on Circuits and Systems}. YEAR = {2019}}
Due to the advent of deep sub-micron technologies, statistical (in addition to temperature and supply voltage) variations aware estimation of leakages power has become prominent. Also, estimation of leakage currents at SPICE level guarantees the most accurate results, however not feasible means in high complexity ICs. This performs adversely for Monte-Carlo iterations for statistical analysis. In this paper we introduced an accurate machine learning technique to model statistical and operating variation aware estimation from Artificial Neural Network and regression based Multivariate Polynomial Regression which exhibits innately faster computation and attained error less than 1% for the targeted 16nm FinFET technology node although model is black box for any technology. The accuracy of the proposed technique has been tested over several basic cells and estimation of the complex circuits have been carried out utilizing the pre-modelled basic cells.
A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications
HULUVALLAY MOHAMMED ASHFAKH ALI,Lade Sai Kiran,Arpan Jain,Zia Abbas
IEEE Transactions on Very Large Scale Integration Systems, VLSI-SoC, 2019
@inproceedings{bib_A_47_2019, AUTHOR = {HULUVALLAY MOHAMMED ASHFAKH ALI, Lade Sai Kiran, Arpan Jain, Zia Abbas}, TITLE = {A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications}, BOOKTITLE = {IEEE Transactions on Very Large Scale Integration Systems}. YEAR = {2019}}
A sub 1−V , ultra low power temperature sensor has been implemented in TSMC 180 nm. The architecture is digital friendly since it creates a pulse width modulated wave instead of voltage. It uses proportional to absolute temperature(PTAT) characteristics of resistance to generate PTAT delay. Temperature to delay conversion depends only on passive elements, thereby making the circuit insensitive to supply variations. Line sensitivity of 0.23 ◦C/V is achieved for a wide supply range of 0.7−3.6 V . A non linearity error of less than 0.8 ◦C is measured for −55 to 125 ◦C using linear fit curve. This occupies an area of 0.82 mm2 and consumes a power of 47 nW at 0.8 V supply.
Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models
DEEPTHI AMURU,Andleeb Zahra,Zia Abbas
International Symposium on VLSI Design and Test, VDAT, 2019
@inproceedings{bib_Stat_2019, AUTHOR = {DEEPTHI AMURU, Andleeb Zahra, Zia Abbas}, TITLE = {Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models}, BOOKTITLE = {International Symposium on VLSI Design and Test}. YEAR = {2019}}
With the technology scaling down to sub-50 nm regime, the necessity of process variation aware estimation of Leakage Power is emphasized for robust digital circuit design. Variations in Leakage power results in a large increase in the variation of total power dissipation. This paper presents a Regression based estimation of leakage powers and total power dissipation in nanoscale standard cell-based designs that show an impressive speed-up advantage with respect to analog SPICE-level simulation. We propose a statistical variation aware estimation model through a Multivariate Linear Regression (MLR) and Multivariate Polynomial Regression (MPR) techniques. Exhaustive tests report shows MPR technique outperforms MLR technique in estimating the leakage and total power for the targeted 16 nm CMOS technology with negligible error (<1%). The proposed methodology works as black box i.e. equally valid for 16 nm, 22 nm and 45 nm technology nodes.
PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit Design
PRATEEK GUPTA,Gourishetty Shirisha,Harshini Chowdary Mandadapu,Zia Abbas
IEEE International Symposium on Circuits and Systems 2019, ISCAS, 2019
@inproceedings{bib_PVT__2019, AUTHOR = {PRATEEK GUPTA, Gourishetty Shirisha, Harshini Chowdary Mandadapu, Zia Abbas}, TITLE = {PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit Design}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems 2019}. YEAR = {2019}}
Enormous increase in process variations (due to progressive CMOS technology scaling) along-with the temperature and supply voltage variations are severely degrading the fabrication outcome of digital circuits i.e. circuits are not accomplishing the specification bounds of the required performances. Therefore, process and operating variations aware optimization has become a very essential task in VLSI design. Moreover, many specifications in a circuit have challenging trade-offs, hence demand effective optimization skills. With this vision, this paper presents optimization algorithm based robust transistor sizing for various nanoscale CMOS digital circuits. The objective is to minimize the static i.e. leakage power without degrading the operating frequency (i.e. keeping the propagation delays in bound) and area. The reported results are shown for 32nm CMOS Metal gate High-k model parameters, however methodology is equally valid for further scaled technology nodes. The Overall reduction in leakage power obtained is up to 88% keeping bound on the critical path delay. The temperature range and supply voltage has been taken between −55◦C to +125◦C (for automotive applications) and 0.90V to 1.10V (±10% variations) respectively at 3-sigma design.
A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications
Arpan Jain,HULUVALLAY MOHAMMED ASHFAKH ALI,Lade Sai Kiran,Zia Abbas
IEEE International Symposium on Circuits and Systems, ISCAS, 2019
@inproceedings{bib_A_Hi_2019, AUTHOR = {Arpan Jain, HULUVALLAY MOHAMMED ASHFAKH ALI, Lade Sai Kiran, Zia Abbas}, TITLE = {A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications}, BOOKTITLE = {IEEE International Symposium on Circuits and Systems}. YEAR = {2019}}
In this paper, a highly stable all CMOS current reference against temperature and supply variation is proposed. Current reference of 5µA and 50nA has been designed for low power and ultra-low power applications respectively. The reference architecture is based on ratio between the PTAT voltage and the PTAT resistance. The process insensitive temperature compensation is accomplished by dividing TC of voltage with process insensitive TC of resistor. A high PSRR, process independent voltage reference is designed for PTAT voltage. N-poly on chip resistor is used for PTAT resistance. The proposed current reference is implemented in 0.18-µm TSMC technology. The architecture achieved PSRR of 74dB and line sensitivity of 0.05% works at supply voltage variation from 1.4V to 3.6V. The current reference of 5µA and 50nA attain temperature coefficient of 11.6 ppm/oC and 12.2 ppm/oC respectively for the temperature variation of -55oC to 125oC.
Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms
PRATEEK GUPTA,Harshini Chowdary Mandadapu,Gourishetty Shirisha,Zia Abbas
International Symposium on Quality Electronic Design, ISQED, 2019
@inproceedings{bib_Robu_2019, AUTHOR = {PRATEEK GUPTA, Harshini Chowdary Mandadapu, Gourishetty Shirisha, Zia Abbas}, TITLE = {Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms}, BOOKTITLE = {International Symposium on Quality Electronic Design}. YEAR = {2019}}
In this paper, the optimal transistor sizing of the digital cells has been obtained using Simulated Annealing algorithm and an Artificial Bee Colony algorithm and their results have been compared with nominal results for various nanoscale CMOS digital circuits. The goal is to minimize the leakage power keeping the other performance parameters such as propagation delays and the area in the bound. The simulations are done using HSPICE tool for 45nm and below using Metal gate High k Predictive Technology Model cards. To make sure of the unaffected working of all cells in the automotive applications, the temperature range and supply voltage has been taken between −55oC to 125oC and 0.95V to 1.05V respectively. The Overall reduction in leakage power achieved in the logic cells is up to 70% without any penalty in the critical path delay.
Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power
PRATEEK GUPTA,SHUBHAM KUMAR,Zia Abbas
International Symposium on VLSI Design and Test, VDAT, 2018
@inproceedings{bib_Opti_2018, AUTHOR = {PRATEEK GUPTA, SHUBHAM KUMAR, Zia Abbas}, TITLE = {Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power}, BOOKTITLE = {International Symposium on VLSI Design and Test}. YEAR = {2018}}
In this paper, two one-bit full adder design techniques are explored for reduced power consumption in standby mode. The proposed algorithm based techniques compute optimal transistor sizing for variable operating conditions (temperature, supply voltage) to achieve desirable leakage power and speed for a full-adder circuit. Both techniques use ‘SLEEP’ signal to drive full adder circuit to lower standby mode leakage state without even degrading the performances in active mode. The investigation has been carried out for 45 nm, 32 nm, 22 nm Metal Gate High-K PTM models and all the simulation characterizations are carried out using HSPICE simulation tool. Performance comparison of both techniques after optimization has been done over a complete range temperature (−40 ∘ C−125 ∘ C) and ±5% variation in supply voltage. The resultant designs are tested on large full-adder based digital circuits to analyze the reduced standby leakage power. The results show that up to 97% of standby leakage reduction can be obtained with (0.4–15)% delay overhead using the proposed methods of full-adder design.
Voltage Level Adapter Design for High Voltage Swing Applications in CMOS Differential Amplifier
HULUVALLAY MOHAMMED ASHFAKH ALI,Arpan Jain,Zia Abbas
International Symposium on VLSI Design and Test, VDAT, 2018
@inproceedings{bib_Volt_2018, AUTHOR = {HULUVALLAY MOHAMMED ASHFAKH ALI, Arpan Jain, Zia Abbas}, TITLE = {Voltage Level Adapter Design for High Voltage Swing Applications in CMOS Differential Amplifier}, BOOKTITLE = {International Symposium on VLSI Design and Test}. YEAR = {2018}}
This work focuses on circuit level technique that achieves high swing in single ended output differential amplifiers like differential amplifier with active current mirror load, telescopic cascode, folded cascode etc. This technique is designed in such a manner that it can be visualized as a 2-terminal black box. Now, these 2-terminals can be connected to the conventional single ended differential amplifiers enhancing their swing without degrading other parameters like gain, bandwidth, CMRR etc. This black box achieves its performance consuming less power and minimum circuitry area. All the simulation characterization and validation has been made through UMC 180 nm technology node in Cadence.
LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16nm CMOS Circuits
Zia Abbas,Andleeb Zahra,Mauro Olivieri
International Symposium on VLSI Design and Test, VDAT, 2018
@inproceedings{bib_LEAD_2018, AUTHOR = {Zia Abbas, Andleeb Zahra, Mauro Olivieri}, TITLE = {LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16nm CMOS Circuits}, BOOKTITLE = {International Symposium on VLSI Design and Test}. YEAR = {2018}}
Fast-computable and accurate leakage models for state of the art CMOS digital standard cells is one of the most critical issues in present and future nano-scale technology nodes. It is further interesting if such model can calculate leakage currents not only at initial circuit life but also over the years based on Bias Temperature Instability (BTI) aging mechanism, which increases the threshold voltage over the years – thus mitigating leakage – but in turn degrades circuit speed. A reliable quantification of such aging-induced leakage mitigation opens the way to effective trade-off techniques for compensating speed degradation while maintaining leakage within specification bounds. The presented logic level leakage characterization and estimation technique, currently implemented as VHDL packages, shows more than 103 speed-ups over HSPICE circuit simulation and exhibits less than 1% error over HSPICE. We report BTI aging aware leakage current estimation for ten years at 25 °C and 90 °C in 16 nm CMOS technology, and we analyze how such leakage reduction trend can be traded off to improve the degraded circuit speed over time.
Multi-Objective Optimization Algorithm Based Transistor Sizing for Improved Power-Delay-Area in Digital Circuits
PRATEEK GUPTA,Zia Abbas
India Council International Conference, INDICON, 2018
@inproceedings{bib_Mult_2018, AUTHOR = {PRATEEK GUPTA, Zia Abbas}, TITLE = {Multi-Objective Optimization Algorithm Based Transistor Sizing for Improved Power-Delay-Area in Digital Circuits}, BOOKTITLE = {India Council International Conference}. YEAR = {2018}}
The goal of this paper is to obtain the robust transistor sizing of the digital logic circuits by minimizing the leakage power keeping the other performance parameters such as propagation delays and area in the bound. To perform such action, Simulated Annealing based Multi-Objective Optimization algorithm has been implemented and further improved the reduction in leakage power using Gradient Descent (MO-SAGRAD).The algorithms are implemented in python and the performance parameters are computed using HSPICE tool at 45nm, 22nmtechnology nodes with Metal Gate High K PTM model cards. Toensure the unruffled functioning of the cells in the automotive applications, the temperature range has been taken between−55oCto125oCrespectively and the supply voltage range istaken as 0.95V to 1.05V for 45nm and 0.76V to 0.84V for22nm technology node. The Overall reduction in leakage power achieved in the logic cells is up to 58% without any penalty in the critical path delay.
Geometry Scaling Impact on Leakage Currents in FinFET Standard Cells Based on a Logic-Level Leakage Estimation Technique
Zia Abbas,Dr. Andleeb Zahra,Mauro Olivieri,Antonio Mastrandrea
Microelectronics, Electromagnetics and Telecommunications, ICMEET, 2018
@inproceedings{bib_Geom_2018, AUTHOR = {Zia Abbas, Dr. Andleeb Zahra, Mauro Olivieri, Antonio Mastrandrea}, TITLE = {Geometry Scaling Impact on Leakage Currents in FinFET Standard Cells Based on a Logic-Level Leakage Estimation Technique}, BOOKTITLE = {Microelectronics, Electromagnetics and Telecommunications}. YEAR = {2018}}
Static power consumption is one of the most critical issues in CMOS digital circuits, and FinFET technology is being recognized as a valid solution for the problem. In this chapter, we utilize a logic-level leakage current estimation technique relying on an internal node voltage-based model. The model is implemented in the form of VHDL packages. By utilizing the capability of the model, the behavior of major leakage component has been analyzed separately for FinFET technology scaling over single- and multi-stage digital standard cells.
Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations
Zia Abbas,Mauro Olivier,Andreas Ripp
Journal of Computational Electronics, JCE, 2016
@inproceedings{bib_Yiel_2016, AUTHOR = {Zia Abbas, Mauro Olivier, Andreas Ripp}, TITLE = {Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations}, BOOKTITLE = {Journal of Computational Electronics}. YEAR = {2016}}
We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. The final design solutions present transistor sizing, which depart from intuitive transistor sizing criteria and show dramatic yield improvements, which have been verified by Monte Carlo SPICE analysis.
Optimal nbti degradation and pvt variation resistant device sizing in a full adder cell
Zia Abbas,Mauro Olivier, Usman Khalid, Andreas Ripp,Michael Pronath
International Conference on Reliability, Infocom Technologies and Optimization, ICRITO, 2015
@inproceedings{bib_Opti_2015, AUTHOR = {Zia Abbas, Mauro Olivier, Usman Khalid, Andreas Ripp, Michael Pronath}, TITLE = {Optimal nbti degradation and pvt variation resistant device sizing in a full adder cell}, BOOKTITLE = {International Conference on Reliability, Infocom Technologies and Optimization}. YEAR = {2015}}
Aging phenomena, on top of process variations along with temperature and supply voltage variations, translate into complex degradation effects on the required performance and yield of nanoscale circuits. The proposed paper focuses on the development of mathematically optimal circuit sizing for yield maximization on the case study of a CMOS full adder circuit. The final cell design is robust against NBTI aging effects, impact of statistical (global and mismatch) and operating variation of temperature and supply voltage. Monte Carlo analysis has been carried out to verify the estimated yields. The demonstrated technique can be extended to a library of optimally designed digital cells
Variability Aware Modeling of SEU Induced Failure Probability of Logic Circuit Paths in Static Conditions
Usman Khalid,Antonio Mastrandrea,Zia Abbas,Mauro Olivieri
International Conference on Reliability, Infocom Technologies and Optimization, ICRITO, 2015
@inproceedings{bib_Vari_2015, AUTHOR = {Usman Khalid, Antonio Mastrandrea, Zia Abbas, Mauro Olivieri}, TITLE = {Variability Aware Modeling of SEU Induced Failure Probability of Logic Circuit Paths in Static Conditions}, BOOKTITLE = {International Conference on Reliability, Infocom Technologies and Optimization}. YEAR = {2015}}
Voltage noise can lead to various errors such as dynamic and permanent, which are directly associated to circuit-level reliability issues. Variability in process parameters directly affects the probability of failures associated to voltage noise. Yet, the evaluation of the probability of failures by SPICE level Monte Carlo simulation is prohibitively time-consuming. This work proposes a technique to characterize the input noise and process variations in order to estimate failure probability in a logic circuit path composed of combinational cells and registers. The method allows to correctly estimate the order of magnitude of the probability of failures and to evidence the influence of process variations, while reaching >104 speedup versus SPICE.
